NAND Flash Memory Charge-Packet Programming for Breakdown Control
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Solution Overview
Problem
The challenge of scaling down memory cell pitch in NAND flash memory leads to increased risk of dielectric breakdown between word lines due to higher electric fields and voltage differences, which conventional solutions like increasing pass bias cannot effectively address without causing program disturbance.
Innovation Solution
A method involving the formation of charge packets in a semiconductor channel layer, followed by controlled injection into memory cells using small differential voltages, where a first gate controls the channel potential and programming voltage is applied simultaneously to all word lines, allowing for efficient and selective programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell pitch is scaled down to increase bit density, then the bit density is improved, but the risk of dielectric breakdown between word lines increases due to higher electric fields and voltage differences
Solution Approach 1:
The patent applies preliminary action by forming charge packets in the channel layer before the actual programming operation. The channel layer is pre-charged with electrons that will be subsequently injected into the memory cells. This separation of charge formation and charge injection allows the use of lower programming voltages, reducing the voltage difference between adjacent word lines and thereby minimizing dielectric breakdown risk while maintaining high bit density
Solution Approach 2:
The channel layer serves as an intermediary between the external voltage source and the memory cells. Instead of directly applying high voltage to program memory cells, the channel layer acts as a mediator that stores charge temporarily and releases it controllably. This intermediary mechanism enables programming with reduced voltage differences between word lines, solving the dielectric breakdown problem in high-density configurations
2Productivity
If the pass bias is increased to compensate for decreased capacitive coupling, then the programming operation is improved, but the program disturbance becomes unacceptable
Solution Approach 1:
The patent uses preliminary action by pre-forming charge packets in the channel layer before programming. This allows the memory cells to be programmed using smaller voltage differences without requiring high pass bias. The charge packets are ready to be injected as soon as the programming voltage is applied, enabling efficient programming with minimal disturbance to neighboring cells
Solution Approach 2:
The patent changes the programming approach by transitioning from direct high-voltage programming to a two-stage process: first forming charge packets at lower voltage, then injecting them at controlled voltage differences. This parameter change in the programming methodology reduces program disturbance while maintaining programming efficiency
3Quantity of substance
If the inter-gate spacing is reduced to increase bit density, then the bit density is improved, but the electric fields increase for a given voltage difference, further increasing dielectric breakdown risk
Solution Approach 1:
By forming charge packets in advance in the channel layer, the patent enables programming with smaller voltage differences. This preliminary charge formation reduces the voltage difference between word lines during programming, which directly reduces the electric field strength in the reduced inter-gate spacing regions, thereby minimizing dielectric breakdown risk in high-density structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the risk of dielectric breakdown and enables faster, bit-selective programming with controlled charge concentration, achieving efficient programming of memory cells with minimal voltage differences between adjacent word lines.
Implementation Method 1
Quantum tunneling is utilized to change the charge carrier concentration, thereby writing or erasing information into or from a memory cell
Implementation Method 2
applying a first voltage to the first gate and a pass voltage to one or more of the word lines to allow charges to inject into the channel layer
Implementation Method 3
applying a programming voltage to one or more of the word lines to move the one or more charge packets from the channel layer into the one or more memory cells
Data Source
AI summary
This disclosed technology relates to a programmable NAND flash memory and a method for operating the NAND flash memory. The method comprises applying a first voltage to the first gate and a pass voltage to one or more word lines to allow charge to inject into the channel layer and form charge packets. Each charge packet can be arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.