Charge Pump Amplitude Modulation for Voltage Drop Compensation
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Solution Overview
Problem
Conventional charge pumps face inefficiencies due to voltage drops across transistors, which reduce output voltage and increase layout area and power consumption, especially when generating low voltage outputs, and existing threshold voltage cancellation techniques have limitations such as increased complexity and power consumption.
Innovation Solution
A threshold voltage cancellation section with the same structure as the main charge pump section is introduced, using mirrored nodes to control the transistors and reduce voltage drops, and amplitude modulation of gate clock signals to minimize quiescent power consumption, particularly effective in voltage doubler-type charge pumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional charge pump switching process is used, then DC output voltage can be generated larger or lower than input voltage, but voltage drops across transistors reduce output voltage and increase power consumption
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate clock signal amplitude based on operating conditions. The gate clock signal amplitude is modified to compensate for transistor voltage drops, thereby maintaining output voltage while reducing power consumption. This is achieved by changing the voltage amplitude parameter of the gate clock signal rather than using fixed amplitude signals.
Solution Approach 2:
The patent implements feedback mechanisms where the charge pump monitors its operating state and adjusts the gate clock signal amplitude accordingly. The system uses feedback from the operating conditions to dynamically modify the gate clock signal parameters, enabling the charge pump to adapt to varying load conditions and minimize power losses across transistors.
2Power
If conventional charge pump design is used, then voltage multiplication can be achieved, but layout area increases
Solution Approach 1:
The patent applies dynamics by transitioning from static, fixed-amplitude gate clock signals to dynamic, adjustable-amplitude signals. The gate clock signal amplitude is dynamically adapted based on the charge pump's operating state, allowing the same hardware to achieve voltage multiplication across different operating conditions without requiring additional layout area for multiple fixed configurations.
Solution Approach 2:
The patent achieves universality by designing a gate clock signal generation mechanism that can operate across multiple operating conditions using a single circuit configuration. The adjustable amplitude gate clock signal generator serves multiple functions - it can adapt to different load conditions, maintain voltage multiplication across varying input voltages, and eliminate the need for separate circuits for different operating modes, thereby reducing overall layout area.
3Power
If threshold voltage cancellation techniques are applied, then voltage drops can be reduced, but complexity and power consumption increase
Solution Approach 1:
The patent applies parameter changes by adjusting the amplitude parameter of the gate clock signal to compensate for threshold voltage effects. Rather than introducing complex threshold voltage cancellation circuits, the invention modifies the voltage amplitude parameter of the existing gate clock signal to achieve similar compensation effects, thereby reducing output voltage drops without significantly increasing circuit complexity.
4Loss of energy
If gate clock signal amplitude is increased to maintain output voltage, then power efficiency improves, but quiescent power consumption increases
Solution Approach 1:
The patent applies dynamics by making the gate clock signal amplitude adjustable and adaptive rather than fixed. The system dynamically adjusts the gate clock signal amplitude based on operating conditions - using higher amplitudes when needed to maintain power efficiency during active operation, and reducing amplitudes during quiescent states to minimize power consumption. This dynamic adaptation resolves the contradiction between power efficiency and quiescent power consumption.
Data Source
AI summary
Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.