Charge Pump Circuit Assist Switches for Heavy-Load Voltage Stability

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Solution Overview

Problem

Existing charge pump circuits in semiconductor memory devices face issues with sudden output voltage drops due to heavy current loading, causing switches to be erroneously turned off and leading to ineffective operation.

Innovation Solution

Incorporation of assist switches and capacitors in the charge pump circuit to maintain a higher gate-source voltage difference, preventing switches from turning off during heavy current loading, thereby sustaining larger current loads and improving driving capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If charge pump circuit operates under heavy current loading, then current driving capability is improved, but output voltage drops suddenly causing switches to turn off erroneously

Engineering Contradiction:
Improvecurrent driving capabilityVSAvoidswitch operation stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent introduces a voltage regulation module as an intermediary component between the charge pump circuit and the output. This module includes a regulation transistor whose gate voltage is dynamically adjusted based on the output current load. The regulation transistor acts as a mediator that compensates for voltage drops by providing additional voltage support when heavy loading occurs, preventing the switches from turning off erroneously while maintaining stable output voltage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the gate voltage of the regulation transistor is controlled according to the output current load. The control circuit monitors the output conditions and adjusts the gate voltage accordingly - increasing gate voltage when heavy loading is detected to prevent voltage drops, and reducing it when loading is light. This feedback control ensures switches remain properly activated under varying load conditions while maintaining efficient charge pump operation.

Inventive Principle:
Principle #23Feedback

2Device complexity

If charge pump circuit uses traditional switch configuration, then device complexity is reduced, but driving capability under heavy load deteriorates

Engineering Contradiction:
Improvecircuit structure simplicityVSAvoiddriving capability
Core Design Contradiction:
Device complexityVSPower

Solution Approach 1:

The regulation transistor in the voltage regulation module serves multiple functions simultaneously: it compensates for voltage drops under heavy loading, stabilizes the output voltage, prevents switch misoperation, and adjusts its operation based on feedback from the output current. This multi-functional component enhances driving capability without requiring separate dedicated circuits for each function, thereby maintaining relatively simple device complexity while achieving improved performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250350201A1Charge Pump Circuits and Methods for Operating The Same
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250350201A1 patent drawing
  • US20250350201A1 patent drawing
  • US20250350201A1 patent drawing

AI summary

A circuit includes first and second transistors coupled in series, respective gate terminals of which are coupled to a first node to receive a first signal through a first capacitor; third and fourth transistors coupled in series, respective gate terminals of which are coupled to a second node to receive a second signal logically inverse to the first signal through a second capacitor; a fifth transistor having its source/drain terminals coupled between the gate terminal of the first transistor and the first node; a sixth transistor having its source/drain terminals coupled between the first node and the gate terminal of the second transistor; a seventh transistor having its source/drain terminals coupled between the gate terminal of the third transistor and the second node; and an eighth transistor having its source/drain terminals coupled between the second node and the gate terminal of the fourth transistor.