Charge Pump Slew Rate Control via Dynamic Clock Frequency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing charge pump circuits for floating gate non-volatile memories face challenges in achieving target erase voltage across varying memory block sizes without overshooting, which can lead to catastrophic failure, especially for larger blocks, and current solutions either complicate the circuit or increase costs.
Innovation Solution
A simplified charge pump system with a capacitive voltage divider and a comparator circuit that adjusts the clock frequency based on memory block select signals to control the slew rate, ensuring the voltage ramps down to the target level without exceeding the breakdown voltage, using a frequency divider and conversion logic to manage capacitive loads effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the charge pump uses a fixed clock frequency designed for the largest memory block, then it achieves the target voltage for large blocks, but it causes significant overshoot for smaller blocks leading to catastrophic failure
Solution Approach 1:
The charge pump system dynamically adjusts the clock frequency based on the detected memory block size. The control circuit receives block select signals, determines the capacitive load, and accordingly selects different clock frequencies from a bank of divided clocks. This dynamic adaptation allows the system to optimize the voltage ramp rate for each specific block size, preventing overshoot in smaller blocks while maintaining adequate performance in larger blocks.
Solution Approach 2:
The system changes the operational parameter (clock frequency) based on the memory block size. By dividing the main clock signal into multiple frequencies and selecting the appropriate one based on block capacitance, the system adjusts the slew rate of the voltage ramp to match the specific capacitive load, thereby avoiding overshoot conditions that would destroy memory cells.
2Reliability
If a sophisticated control circuit or complicated comparator circuit is used to prevent voltage overshoot, then memory cell destruction is avoided, but the circuit complexity and manufacturing cost increase significantly
Solution Approach 1:
The system performs preliminary detection of the memory block size before initiating the charge pump operation. The control circuit analyzes the block select signals to determine which block is active and predicts the capacitive load. Based on this preliminary information, the system pre-selects the appropriate clock frequency, avoiding the need for complex real-time monitoring and adjustment mechanisms during the actual charge pump operation.
Solution Approach 2:
Instead of using a single complex comparator circuit that continuously monitors voltage, the system uses multiple simple frequency-divided clock signals that represent different capacitive load scenarios. This approach replaces a complex continuous control mechanism with a set of discrete, pre-calibrated frequency options, simplifying the overall control architecture while maintaining reliability.
3Reliability
If a large stability capacitor is added to the charge pump circuit to prevent overshoot, then voltage stability is improved, but the IC space consumption increases and manufacturing cost rises
Solution Approach 1:
Rather than adding physical capacitance to stabilize the voltage, the system stabilizes the voltage by changing the temporal parameter (clock frequency) to match the capacitive load. This approach achieves voltage stability through dynamic frequency adjustment rather than through increased capacitance, thereby avoiding the need for additional large capacitors that would consume valuable IC space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for achieving the target erase voltage for all memory blocks with a simple and inexpensive comparator circuit, preventing overshoot and ensuring the stability of the memory device, while maintaining performance levels by adjusting the clock frequency in accordance with the selected memory block capacitance.
Implementation Method 1
a charge pump circuit which pumps charge to the charge node at a rate based on the frequency of the first clock
Implementation Method 2
The charge pump circuit includes a capacitive voltage divider having a first node coupled to the charge node and a second node providing a divided voltage signal
Implementation Method 3
a comparator circuit having an input coupled to the second node of the capacitive voltage divider and providing a control signal
Data Source
AI summary
A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.