Charge Pump Clock-Rate Control for Low-Temperature Memory Erase
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Solution Overview
Problem
In semiconductor memory systems, particularly non-volatile memory devices, power supply current peaks during erase operations at low temperatures exceed specified limits, and latent manufacturing defects can corrupt data stored in memory cells, especially in densely packed arrays with multi-plane structures.
Innovation Solution
A control circuit is implemented to selectively reduce the clock rate of charge pump circuits during erase operations, thereby managing power supply current and minimizing data corruption by adjusting voltage levels based on temperature and operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If charge pump circuits operate at high speed during erase operations, then erase operation speed is improved, but power supply current peaks exceed specified limits
Solution Approach 1:
The charge pump circuit dynamically adjusts its operating speed based on temperature conditions. At lower temperatures, the clock rate is reduced to prevent power supply current peaks, while at higher temperatures, normal operating speed is maintained for optimal erase performance. This dynamic adaptation resolves the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the operating parameter (clock rate) of the charge pump circuit based on temperature thresholds. When temperature falls below a predetermined threshold, the clock rate is modified to reduce power consumption, thereby resolving the contradiction between high-speed operation and power limits.
2Productivity
If charge pump circuits operate at high speed, then productivity is improved, but data corruption from latent defects increases
Solution Approach 1:
The system dynamically adjusts charge pump speed based on temperature conditions to balance productivity and reliability. By reducing speed at low temperatures where latent defects are more prevalent, data corruption is minimized while maintaining high-speed operation at higher temperatures where reliability is better.
Solution Approach 2:
The control circuit monitors temperature conditions and provides feedback to adjust charge pump operation accordingly. This feedback mechanism ensures that erase operations adapt to environmental conditions, reducing data corruption risks from latent defects while maintaining overall productivity.
3Quantity of substance
If memory cells are packed more densely, then storage capacity is improved, but maintaining data integrity becomes more challenging
Solution Approach 1:
The patent adjusts charge pump operating parameters based on temperature to protect densely packed memory cells from data corruption. By reducing operational stress at low temperatures, the system maintains data integrity in high-density storage configurations.
Data Source
AI summary
An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.