Multi-Stage Charge Pump Clock Level Shifting for Smaller Chip Area
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Solution Overview
Problem
Multi-stage charge pumps require significant chip area and are complex due to the need for additional capacitance and biasing in downstream stages, which complicates design and increases power consumption.
Innovation Solution
The implementation of a multi-stage charge pump with stage-specific voltage level-shifted clock signal-inverted pairs, eliminating the need for additional series-connected capacitors or higher voltage capacitors in downstream stages, thereby reducing complexity and chip area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-stage charge pumps use series-connected capacitors in downstream stages to achieve voltage boost, then voltage output is improved, but device complexity and chip area increase significantly
Solution Approach 1:
The charge pump is divided into multiple stages, each generating voltage at a specific level. The first stage generates voltage at 2*VDD, the second stage at 3*VDD, and so on. Each stage operates independently with its own clock signals, eliminating the need for series-connected capacitors across stages and reducing overall circuit complexity while maintaining the voltage boosting function.
Solution Approach 2:
Each charge pump stage is designed with local optimization, using capacitors sized and configured specifically for that stage's voltage level. The clock signals are also optimized locally for each stage, with frequency and amplitude tailored to the specific voltage requirements of that stage, improving efficiency without requiring complex inter-stage capacitor networks.
2Power
If multi-stage charge pumps use series-connected capacitors in downstream stages, then voltage boost is achieved, but chip area consumption increases
Solution Approach 1:
By segmenting the charge pump into independent stages, each stage can use its own dedicated capacitors rather than requiring series-connected capacitors across all stages. This segmentation allows for more efficient use of chip area, as capacitors can be distributed and sized according to local needs rather than requiring a large series network.
Solution Approach 2:
The patent transitions from a planar series-connected capacitor arrangement to a multi-dimensional architecture where clock signals are level-shifted to different voltage domains. This dimensional change in signal control allows independent stage operation, eliminating the need for series capacitors and reducing chip area requirements.
3Power
If multi-stage charge pumps are designed with additional capacitance in downstream stages, then voltage output is improved, but power consumption increases
Solution Approach 1:
Each charge pump stage uses capacitors optimized for its specific voltage level and operational requirements. The first stage uses capacitors sized for 2*VDD operation, the second stage for 3*VDD, and so on. This local optimization ensures that each stage consumes minimal power for its voltage generation, avoiding the excessive power consumption that would result from using oversized series-connected capacitors across all stages.
Solution Approach 2:
The patent changes the operational parameters of each stage, specifically the clock signal frequency and amplitude, to match the voltage level of that stage. This parameter optimization allows each stage to operate efficiently at its designated voltage level, reducing overall power consumption while maintaining the desired voltage output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces circuit complexity and chip area usage while improving reliability by eliminating the need for additional capacitance and simplifying the design of multi-stage charge pumps.
Implementation Method 1
The clock generator can receive the first clock signal and the inverted first clock signal and can output a second clock signal and an inverted second clock signal that are voltage level-shifted (higher) relative to the first clock signal and the inverted second clock signal
Data Source
AI summary
A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.