Charge Pump Gate Boosting for Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitances in charge pump devices, such as those using MOS transistors, lead to performance issues like short circuits and reduced output voltage due to parasitic capacitive dividers and incomplete switching of transistors.
Innovation Solution
The implementation of additional gate boosting capacitors and selective coupling of control inputs of valve transistors with input or output terminals, utilizing non-overlapping clock signals to ensure proper switching and mitigate parasitic capacitance effects, is employed to improve charge pump efficiency and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOS transistors are used in charge pump circuits, then the charge pump can be implemented with standard semiconductor devices, but parasitic capacitances of the transistors adversely affect the performance of the charge pump
Solution Approach 1:
The patent extracts the problematic parasitic capacitances from the transistor structure by introducing separate boosting capacitors connected to the gate terminals. These external capacitors are specifically designed to compensate for the parasitic effects, allowing the MOS transistors to be used while mitigating their harmful capacitance effects through the addition of dedicated compensation elements.
Solution Approach 2:
The patent introduces boosting capacitors as intermediary elements between the transistor gates and the charge pump nodes. These capacitors act as mediators that store and transfer charge to counteract the parasitic capacitance effects, enabling the MOS transistors to function properly despite their inherent parasitic properties.
2Device complexity
If standard transistor switching is used, then the circuit structure remains simple, but incomplete switching of transistors occurs due to parasitic capacitances
Solution Approach 1:
The patent applies preliminary action by pre-charging the gates of the transistors through boosting capacitors before the actual switching operation. This preliminary charge injection ensures that the transistors achieve complete switching states despite the presence of parasitic capacitances that would otherwise prevent full voltage swing and incomplete conduction.
Solution Approach 2:
The patent changes the voltage parameters at the transistor gates by introducing additional charge through boosting capacitors. This parameter modification ensures that the gate voltages reach sufficient levels to overcome parasitic capacitance effects and achieve complete transistor switching, transforming the incomplete switching state into a complete one.
3Power
If charge is pumped using standard methods, then the basic charge pump function is achieved, but voltage drops across transistors reduce the output voltage
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitances into a beneficial mechanism by using the same capacitance effects to store and transfer additional charge. The boosting capacitors utilize capacitance to inject extra charge into the transistor gates, transforming the parasitic capacitance problem into a useful charge transfer mechanism that compensates for voltage drops and increases output voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces voltage drops across transistors, increases output voltage, and enhances the overall efficiency of the charge pump by ensuring complete switching and minimizing the impact of parasitic capacitances.
Implementation Method 1
The implementation of additional gate boosting capacitors and selective coupling of control inputs of valve transistors with input or output terminals
Data Source
AI summary
Charge-pump devices and corresponding methods are disclosed. A control input of a valve transistor of the charge pump device may be coupled with one of an input terminal or an output terminal via a further transistor.