Charge Pump Layout for 3D Memory Word-Line Voltage Efficiency
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Solution Overview
Problem
As the number of stacked layers of word lines increases in multi-layered memory devices, the size of the charge pump in the voltage generator also increases, affecting efficiency.
Innovation Solution
The layout arrangement of the charge pump is optimized by arranging pumping stages and signal controllers in specific directions relative to through vias, minimizing resistance and maximizing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked layers of word lines is increased to improve integration, then the degree of integration is improved, but the size of the charge pump increases and efficiency deteriorates
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional vertical stacking architecture. Memory cells are arranged in multiple stacked layers with word lines extending vertically through the stack, enabling higher integration density without proportionally increasing the charge pump size. The charge pump is positioned in the peripheral circuit region beneath the memory cell stack, utilizing vertical space efficiently.
Solution Approach 2:
The charge pump circuit is divided into multiple pumping stages (first pumping stage, second pumping stage, etc.), each responsible for specific voltage generation tasks. This segmentation allows distributed placement of pumping capacitors and control circuits, reducing the concentration of large charge pump components in one location and improving overall efficiency while supporting multiple stacked word lines.
2Adaptability or versatility
If the size of the charge pump is increased to support more word lines, then the operating voltage coverage is improved, but the efficiency of the voltage generator deteriorates
Solution Approach 1:
The voltage generator employs dynamically controllable pumping capacitors and charge transfer switches that can be selectively activated based on the required operating voltage. The signal controller adjusts the charging and discharging cycles of individual pumping stages, enabling adaptive voltage generation across different operating conditions without requiring all charge pump components to operate at maximum capacity simultaneously, thus maintaining efficiency.
Solution Approach 2:
The charge pump utilizes multiple pumping stages with different capacitance values and switching frequencies to generate a range of operating voltages. By changing the operational parameters (capacitor charging/discharging rates, switch timing) of individual stages, the system can adapt to different voltage requirements while minimizing energy loss, rather than simply increasing the overall charge pump size.
3Loss of energy
If the layout arrangement of the charge pump is optimized, then the efficiency is improved, but the design complexity increases
Solution Approach 1:
The patent employs an asymmetric layout where the charge pump components are strategically positioned in the peripheral circuit region rather than uniformly distributed. The first and second pumping stages are arranged with different orientations relative to the through vias, optimizing current flow paths and minimizing resistance in critical signal routes. This asymmetric arrangement improves efficiency while the modular stage design keeps the complexity manageable through repetition of functional units.
Solution Approach 2:
Through vias serve as intermediary elements that vertically connect the peripheral circuit region (containing the charge pump) with the memory cell array region above. These vias facilitate efficient current and signal transmission between layers, reducing the need for complex lateral routing and simplifying the overall layout while maintaining high efficiency in voltage delivery to multiple stacked word lines.
Data Source
AI summary
A memory device includes a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array including a plurality of memory cells, and a peripheral circuit region under the memory cell array region, wherein the memory cell array region and the peripheral circuit region are electrically connected by through vias, the peripheral circuit region includes a voltage generator configured to generate an operating voltage to apply to the word lines, the voltage generator includes a pumping capacitor unit configured to charge and pump a voltage based on a clock signal, and a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller includes a clock driver configured to apply a clock signal to the pumping capacitor, and the signal controller is adjacent to the through vias.