Charge-Pump LDO Regulator With Latch-Up Mitigated Voltage Doubler
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Solution Overview
Problem
Conventional charge-pump based LDO regulators suffer from latch-up issues during both steady state and supply ramp-up, which affect the performance of low jitter on-chip clock generators like VCOs due to sensitivity to power supply noise.
Innovation Solution
A latch-up mitigated charge-pump voltage doubler is implemented in the LDO regulator, using a control circuit and power supply timing sequence to ensure the Nwell node of PMOS transistors is at the highest potential, preventing forward biasing of parasitic diodes and mitigating latch-up during transient and steady states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If charge-pump voltage doubler is used to achieve low voltage operation, then power consumption is reduced, but latch-up issues occur during steady state and supply ramp-up
Solution Approach 1:
The patent applies preliminary action by charging the Nwell node to the input voltage level before the clock signal is activated during supply ramp-up. This pre-charging ensures that the Nwell node is at the highest potential before switching operations begin, preventing forward biasing of parasitic diodes and eliminating latch-up conditions before they can occur during the charge pump operation.
Solution Approach 2:
The patent implements preliminary anti-action by using control circuitry to actively prevent the latch-up condition from occurring. The Nwell node is pre-charged to a high potential level that counteracts the tendency of parasitic diodes to forward bias during subsequent switching operations, thereby preemptively neutralizing the harmful latch-up effect before it can manifest.
2Power
If conventional charge-pump circuit is used, then voltage doubling function is achieved, but power supply noise affects clock generators like VCOs
Solution Approach 1:
The patent uses an intermediary approach by introducing a pre-regulator circuit that conditions the input voltage before it reaches the charge pump. This pre-regulator filters and stabilizes the power supply voltage, removing noise and ripple components that would otherwise be amplified by the charge pump and transmitted to sensitive clock generators like VCOs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LDO regulator achieves low noise and wide band power supply rejection, improving power efficiency and reducing latch-up risks, making it suitable for low jitter applications like on-chip oscillators.
Implementation Method 1
an NMOS transistor switch connected to the PMOS switch circuit and configured to receive the input voltage and to charge the Nwell node of the PMOS switch circuit
Implementation Method 2
a voltage doubler including a cross-coupled pair of N-type metal oxide silicon (NMOS) transistors and a pair of charge pump capacitors
Data Source
AI summary
A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.