Charge Pump Level Shifting to Cut Capacitor Breakdown Requirements

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Solution Overview

Problem

Existing semiconductor devices face challenges in efficiently boosting voltage while minimizing increases in manufacturing costs and chip size, particularly due to the need for high-breakdown voltage capacitors when using clock signals with ground voltage levels.

Innovation Solution

A semiconductor device configuration utilizing a level shifter and capacitors to generate clock signals with specific voltage levels, coupled with switch elements and resistors to manage current flow, thereby suppressing the need for high-breakdown voltage capacitors, thus reducing costs and size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a charge pump uses clock signals with ground voltage levels, then voltage boosting function is achieved, but high-breakdown voltage capacitors are required increasing manufacturing costs and chip size

Engineering Contradiction:
Improvevoltage boosting capabilityVSAvoidchip size
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent changes the voltage level parameter of the clock signal from ground level (0V) to a raised level (e.g., 1.8V or higher). By elevating the reference voltage level of the clock signal, the voltage swing required across capacitors is reduced, allowing the use of standard breakdown voltage capacitors instead of high-breakdown voltage types, thereby reducing chip area and manufacturing cost while maintaining the voltage boosting function

Inventive Principle:
Principle #35Parameter changes

2Reliability

If high-breakdown voltage capacitors are used in the charge pump, then voltage boosting reliability is improved, but manufacturing costs and chip size increase

Engineering Contradiction:
Improvevoltage boosting reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent modifies the voltage parameter of the clock signal to operate at an elevated reference level rather than ground level. This parameter change reduces the voltage stress requirements for capacitors, enabling the use of standard, cost-effective capacitor technologies that are easier to manufacture with higher yields, while the voltage boosting reliability is maintained through proper level shifting design

Inventive Principle:
Principle #35Parameter changes

3Reliability

If high-breakdown voltage capacitors are used in the charge pump, then voltage boosting reliability is improved, but chip size increases

Engineering Contradiction:
Improvevoltage boosting reliabilityVSAvoidchip size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By changing the operating voltage parameter of the clock signal to an elevated reference level, the patent reduces the breakdown voltage requirement for capacitors. This allows the use of smaller, standard-voltage capacitors that provide sufficient reliability for voltage boosting applications without the excessive area overhead of high-breakdown voltage capacitor designs

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260081521A1Semiconductor device
Publication Date: 2026.03.19 KK TOSHIBA
  • US20260081521A1 patent drawing
  • US20260081521A1 patent drawing
  • US20260081521A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes: a first switch element having a first end, and a second end and a gate which are mutually coupled in common; a second switch element having a first end, a gate coupled to the gate of the first switch element; a level shifter having input ends to which a first voltage, a voltage of the first end of the second switch element, and a first signal are input, a first output end, and a second output end; a third switch element having a first end coupled to a first node, and a gate controlled by a signal output to the second output end; and a fourth switch element having a first end controlled by a signal output to the first node, a gate coupled to the second output end, and a second end to which the first voltage is input.