Apparatus Without Intermediate Ac Conversion TRIZ Cases

A split-chip regulator places error sensing near the load and power switches on a second chip to improve transient response and voltage control.

Sub-clamp circuits limit switch drain-gate voltage, enabling low-voltage switches in high-bus power conversion with lower loss and cost.

Dynamic clock-frequency limiting cuts light-load ripple and energy loss in switched-capacitor converters while preserving regulation response.

An integrated voltage selector powers the auxiliary circuit from the higher converter node, enabling reverse or bidirectional startup without external boosters.

Cross-feedback between dual charge paths raises gate drive to counter body effect, improving high-voltage output and efficiency.

A voltage clamp and adjusted clock levels stabilize charge pump output faster while cutting amplifier area and power use.

Two coupled step-down stages create a symmetrical voltage drop, lowering isolation stress and easing insulation requirements in switched-mode power supplies.

Multiple reference voltages with adaptive interval timing cut touch panel drive power while keeping signal power and noise immunity in range.

A cascaded boost-buck topology keeps output inductor current continuous to smooth DC voltage transitions, cut ripple, and speed response.

A simplified switched capacitor converter cuts switch and capacitor count, lowers flying-capacitor stress, and reduces PCB area with low loss.

Alternating fly capacitors and load-matched clocking cut charge pump ripple, shrink output capacitor size, and improve power efficiency.

Pre-charged partitioned capacitors let a boost converter settle error voltage instantly and avoid output undershoot during large load changes.

Multiple board-mounted power stages placed around the chip cut impedance, reduce voltage fluctuation, and improve dynamic response.

Forced PWM switching in a memory power control circuit stabilizes internal voltage after low-power exit to prevent initialization failures.

Dynamic on-time and switching-slope adjustment helps a voltage converter react to load changes without output undershoot or overshoot.

A staged buck-boost converter uses an input inductor and unified control to cut ripple-related power loss and extend battery life.

A switched charge circuit replaces fixed-impedance analog crossbars to reconnect neural paths quickly with lower noise, power, and tuning needs.

Autonomous PV converter logic detects open-circuit conditions and discharges the DC bus to bring roof voltage below 30V within 30 seconds.

A switched-capacitor charge pump with a flying capacitor and fine DAC recovers discharge energy to cut MEMS driver power at high voltage.

A hybrid FPGA-DSP SVPWM controller uses lookup-based switching to balance capacitor voltage and minimize harmonics in diode-clamped inverters.

A single-inductor circuit recycles gate charge between power MOSFETs to cut switching losses and ringing in high-frequency DC-DC converters.

A three-state switching sequence keeps inductor current stable at light loads, improving capacitor balancing and demagnetization timing.

Flying-capacitor and auxiliary-switch bootstrap control stabilizes PFM bias power without periodic switching, cutting losses and chip overhead.

Multiple reference voltages and low-voltage detection let a boost converter avoid voltage drops and excessive peak currents under fluctuating supply.

Alternating high-voltage pulses with controlled dwell and frequency improve electroporation precision while limiting damage to surrounding tissue.

A regulating circuit adjusts switching-transistor on-resistance from output feedback to keep charge pump voltage stable under supply variation.

A parallel charge pump and buck stage shifts power delivery by load, improving conversion efficiency from light to heavy demand.

Inverse-coupled inductors and switched-capacitor resonance cut voltage stress, power loss, and inductor size in high-voltage conversion.

A logic circuit monitors supply-node voltage after soft start to trigger AFP mode, preventing transistor damage with low current draw.

A dual-oscillator charge pump uses brief high-frequency bursts to charge an NFET gate quickly while limiting electronic noise.

A bypass capacitor and charge-control circuit stabilize controller power despite output undervoltage and switching-frequency variation.

A series-parallel charge pump and switched-capacitor DAC recover MEMS load energy, cutting dynamic losses at high voltage and frequency.

Independent on-time control keeps SIMO converter switching frequencies in range, reducing light-load ripple and regulated-band noise.

Capacitive voltage division and interleaved switching raise bidirectional DC-DC gain while lowering switch stress and balancing current.

A staged pre-charge raises a charge pump node before full charging, cutting parasitic capacitance loss and improving light-load efficiency.

Series-charge and parallel-discharge capacitors create a stable fractional negative bias that cuts gate leakage, power loss, and noise.

Threshold-based pump enabling matches active charge pumps to load demand, cutting switching power loss while keeping output voltage stable.

Local error signals from multiple driver ICs let a PMIC adapt supply voltage to routing drops, preserving headroom without wasting power.

Using communication-signal power for inverter operation cuts IC power use, avoids extra power ports, and supports stable camera module driving.

An on-chip ramp generator stabilizes COT buck converters without external ESR or TCMF parts, cutting cost, space, and efficiency loss.

Raised clock levels and level shifting boost voltage while avoiding high-breakdown capacitors that increase chip size and cost.

A current mirror and RC filtering shift the converter ground reference to offset parasitic IR drops and keep output voltage stable at low duty cycles.

Selective inductor-based capacitor charging keeps multilevel DC links uniform, cutting circulating currents in parallel inverter systems.

Duty-cycle and load-current sensing infer switching converter input current, preventing voltage drops and abnormal load operation.

Adaptive voltage and temperature tuning stabilizes charge pump oscillator frequency, improving efficiency at high PVT conditions.

A two-stage converter pairs switching and regulation stages to handle varying input power and keep digital circuits operating stably.

Dynamic switching between internal and external negative charge pumps prevents RF supply slumps and preserves fast switch settling.

Dynamic phase reconfiguration lets a multilevel switched capacitor regulator handle wider voltage ranges while balancing current capability and frequency response.

Assist switches and capacitors pre-charge gate nodes to prevent charge pump output drops and switch turn-off under heavy current loads.

Pre-charged capacitors and MOSFET switching supply boost power during constant-current mode, avoiding an oversized PSU for peak loads.

A single switched-capacitor circuit generates two output voltages while limiting switch and capacitor stress to cut power loss and die area.

A phased MOSFET gate-voltage ramp limits startup switching current in step-down charge pumps without needing known switch or capacitor data.

Reverse-current-triggered bottom plate charging cuts parasitic-capacitance ripple in charge pumps while improving efficiency and circuit size.

A staged bootstrapping startup raises switch gate voltage gradually to limit inrush current in step-up charge pumps.

Unified control logic replaces multiple op-amps in a SIMO converter, lowering bandwidth demand and power consumption for low-power outputs.

Holding selected capacitor nodes at a reference voltage in disable mode cuts voltage stress and extends charge pump capacitor life.

A priority-encoded single-inductor control scheme replaces multiple op-amps to cut power use while maintaining multi-output regulation.

A charging circuit boosts a low-capacitance bootstrap capacitor to maintain high-side and low-side switch conduction efficiency at low input voltage.

Flying-capacitor voltage feedback adjusts phase current timing to suppress inter-phase resonances and keep DC-DC converters fast and efficient.

Integrated charge pumps and an inductor replace separate divider and buck stages, cutting power loss and component count in battery power supplies.

An input inductor and reconfigurable topology stabilize switched-capacitor output during high load transients while limiting losses.

Variable phase-trigger timing based on input-output voltage improves power delivery efficiency, lowers heat, and supports phase shedding.

A comparator and deglitch circuit separate genuine power converter faults from inductor ringing to cut false fault signals.

An interleaved switched-capacitor and inductor topology uses a resonant tank to cut ripple and losses while simplifying voltage regulation.

Staggered negative-voltage timing for DRAM word line transistors suppresses power-on overshoot caused by coupling and stabilizes operation.

Extended ramp control uses one ramp and reference duty selection to cut switching loss, ripple, and current draw in buck-boost conversion.

Charge sharing between a fly capacitor and MOSFET parasitic capacitance enables efficient negative voltage generation without a full-rated capacitor.

A control circuit keeps boost-converter PFM above 20 kHz by skipping pulses, cutting audible buzz and improving SNR.

A single bidirectional converter handles battery charging and interface power delivery, cutting circuit size, cost, and power loss.

Adaptive LDO gate-drive circuits limit startup current spikes and support efficient conversion-ratio switching under load.

A series capacitor-buffer path compensates mains voltage variation while converting only a small share of load power to cut losses and size.

A differential switched-capacitor converter boosts gate-drive voltage beyond input rails, enabling smaller, more efficient NMOS RF supply modulators.

Node and output status detectors verify pump and output capacitor charging before full operation, reducing inrush current and switch stress.

A threshold-based protection circuit limits negative current, uses timed high-side switching and tri-state recovery to prevent power switch damage.

Dynamic biasing and load-dependent Miller compensation help an LDO keep fast transient response, high PSRR, and low quiescent current.

A controller switches regulator and charge pump modes as input conditions change, helping the power converter hold a stable output voltage.

A segmented switched-capacitor layout keeps low-side transistors active in 2:1 mode, cutting switching losses and improving battery charging efficiency.

Timed high-side switching and tri-state recovery limit sink current in a switching regulator to prevent power-switch damage and runaway.

A transient enhancement stage samples positive and supply voltages to switch the negative pump input, speeding stable dual-polarity output.

A flying-capacitor and pump-capacitor switch network extends hybrid buck-boost regulation beyond 2VIN with charge balancing.

Charge redistribution in a switched-capacitor loop creates a long, accurate soft-start ramp for DC-DC converters without large on-chip RC elements.

Output voltage is adjusted from the active-core ratio in a blockchain server to cut power waste without compromising computing stability.

A two-stage DC-DC brake coil control uses high release voltage then lower holding voltage to cut heat, power use, and EMC issues.

A switched capacitor stage narrows the auxiliary voltage range in flyback converters, cutting control-circuit power loss across wide outputs.

Interleaved parallel modules with phase-shifted switching smooth input current ripple, enabling smaller input capacitors in high-gain converters.

Selective charge sharing between flying and bootstrap capacitors maintains gate-source voltage across buck and boost modes with fewer parts.

Integrated compensator logic adapts to switched-capacitor ratio changes, keeping loop transfer stable without external feedback reconfiguration.

Dynamic switching between two-inductor and single-inductor modes cuts core loss at mid and low loads while preserving output voltage range.

Capacitor-powered gate drivers cut gate-drive losses and reduce high-voltage transistor needs in switched-capacitor converters.

Feedback control slows one charge pump rail when the other overshoots, countering parasitic-capacitance drift during ramp-up.

A display driver power converting circuit selectively switches between capacitive and inductive DC-DC converters to generate source voltages.

Segmented voltage sensors and differential power converters manage line transients to prevent overvoltage conditions in series-connected load networks.