DRAM Word Line Power Sequencing to Suppress Voltage Overshoot
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Solution Overview
Problem
Voltage overshoot occurs in dynamic random access memory (DRAM) during the power-on process due to a coupling effect, which can lead to operational issues.
Innovation Solution
A memory device with a peripheral circuit comprising a first and second power supply circuit that outputs negative voltages to the substrate and terminal of transistors in the word line drive circuit at different time instants to mitigate the coupling effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is applied to both substrate and terminal simultaneously during power-on, then power-on speed is improved, but voltage overshoot occurs due to coupling effect
Solution Approach 1:
The patent applies preliminary action by first establishing the substrate voltage before applying terminal voltage. The substrate voltage is ramped up first to a first level, and only after this is complete does the terminal voltage begin to ramp up to a second level. This sequencing prevents the coupling effect from causing voltage overshoot while still achieving relatively fast power-on by overlapping the ramp phases.
2Stability of the object's composition
If voltage transition is slowed to reduce overshoot, then voltage stability is improved, but power-on time increases
Solution Approach 1:
The patent employs dynamics by implementing controllable voltage ramping with adjustable slopes. The substrate voltage and terminal voltage are not applied instantaneously but are ramped up at controlled rates. The ramp slope can be dynamically adjusted to balance between minimizing overshoot (slower ramp) and reducing power-on time (faster ramp), allowing optimization for different operating conditions.
Solution Approach 2:
The patent uses periodic action through multi-stage voltage application with distinct phases. The power-on process is divided into periodic stages: first the substrate voltage ramps up, then the terminal voltage ramps up, and each stage can have different timing characteristics. This periodic structuring allows precise control over voltage transitions to achieve both stability and acceptable speed.
3Manufacturing precision
If separate power supply circuits are used for substrate and terminal, then voltage control precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by separating the power supply into distinct circuits for substrate voltage and terminal voltage. Each power supply circuit independently controls its respective voltage, allowing precise control of each voltage level and timing. This segmentation enables the complex voltage control requirements to be met while organizing the circuitry in a modular, manageable way.
Solution Approach 2:
The patent achieves universality by designing power supply circuits that can serve multiple functions. The same power supply circuit architecture can be used for both substrate voltage generation and terminal voltage generation, just with different control parameters and timing. This reduces overall system complexity by reusing proven circuit designs rather than creating entirely separate specialized circuits.
Data Source
AI summary
The present application disclose memory devices, power supply methods, charge pump circuits, and systems. An example memory device includes: a memory cell array including rows of memory cells and a word line coupled to each row of memory cells, and a peripheral circuit coupled with a corresponding row of memory cells via the word line and including a first power supply circuit and a second power supply circuit. The first power supply circuit is configured to start outputting a first voltage to a substrate of a first transistor included in a first word line drive circuit coupled to a first unselected word line at a first time instant. The second power supply circuit is configured to start outputting a second voltage to a terminal of the first transistor at a second time instant. The first time instant is earlier than the second time instant.