Switched-Capacitor Soft-Start Ramp for DC-DC Converters
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Solution Overview
Problem
Existing DC-DC converters face challenges in generating a soft start voltage ramp signal with a long ramping up time on a silicon chip, as prior solutions require large impedance and capacitance elements or complex DACs, leading to increased chip area and variability with process corners and temperature.
Innovation Solution
A switched-capacitor circuit with a voltage buffer and fixed offset generator is used to charge a smaller capacitor in half of the clock cycle, connected to a larger capacitor in the other half, achieving a smooth voltage ramp through charge redistribution without large resistive or capacitance elements, and a low pass filter for consistent accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If large impedance and capacitance elements are used to generate a slow ramping voltage, then the ramping up time is extended, but the chip area increases and variability with process corners and temperature increases
Solution Approach 1:
The patent changes the operating parameters by using switched-capacitor circuits that simulate large resistance values through small physical capacitors switched at specific frequencies. This allows achieving long time constants (large R×C product) without requiring physically large capacitors or resistors on the chip.
Solution Approach 2:
The patent replaces the traditional passive RC time constant approach with an active switched-capacitor mechanism. Instead of relying on physical large-capacity capacitors and high-value resistors, the invention uses small capacitors controlled by switches and clock signals to achieve the same timing function, thereby reducing chip area while maintaining the desired ramping duration.
2Duration of action of moving object
If large impedance and capacitance elements are used to generate a slow ramping voltage, then the ramping up time is extended, but the variability with process corners and temperature increases
Solution Approach 1:
The patent uses switched-capacitor circuits where the time constant is determined by capacitor ratios and switching frequencies rather than absolute resistance and capacitance values. This approach reduces sensitivity to process variations and temperature changes, as capacitor ratios can be manufactured with tighter tolerances than large absolute values.
Solution Approach 2:
By replacing passive RC elements with active switched-capacitor circuits, the patent achieves more stable and predictable timing behavior. The active control mechanism compensates for environmental variations, providing better reliability and consistency across different process corners and temperature conditions compared to passive large-value components.
3Measurement precision
If a DAC is used to achieve slow ramping up time with millivolt level output accuracy, then the ramping precision is improved, but the chip area increases and circuit complexity increases
Solution Approach 1:
The patent achieves precise voltage ramping by controlling the switching frequencies and duty cycles of the capacitor network, rather than using a complex DAC with multiple resistors, switches, and reference voltages. This parameter-based control approach simplifies the circuit while maintaining or improving precision.
Solution Approach 2:
The patent replaces the complex DAC architecture (including bandgap references, resistor ladders, and digital-to-analog conversion logic) with a simpler switched-capacitor voltage ramp generator. This substitution dramatically reduces circuit complexity and chip area while achieving the desired millivolt-level accuracy through controlled charge redistribution.
4Measurement precision
If a DAC is used to achieve slow ramping up time with millivolt level output accuracy, then the ramping precision is improved, but the chip area increases
Solution Approach 1:
The patent achieves precise voltage control through parameter control of the switched-capacitor network (switching frequencies, capacitor ratios, and duty cycles) rather than using a physically large DAC structure. This allows high precision with minimal chip area.
Solution Approach 2:
The patent substitutes the area-intensive DAC structure with a compact switched-capacitor circuit that generates precise voltage ramps through controlled charge transfer. This replacement achieves comparable or superior precision while occupying significantly less chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller, more accurate, and consistently controlled voltage ramp signal with a long ramping up time, reducing chip area requirements and variability, while maintaining precise control over the ramping up time.
Implementation Method 1
The ramp generator embodied in the present invention uses a voltage buffer to sense the ramp voltage. A fixed voltage offset is added to this sensed ramp voltage. The buffered ramp voltage plus the fixed offset is used to charge a smaller capacitor in half of the clock cycle. And in the other half of the clock cycle, this smaller capacitor is disconnected from the ramp voltage buffer and connected to a bigger capacitor which is always connected to the raw signal of the voltage ramp.
Data Source
AI summary
A ramp generator for and method of generating a voltage ramp signal with very long ramping up time on a silicon chip, wherein the method includes a control loop providing a switched-capacitor circuit for generating the voltage ramp signal.