Split-Chip Voltage Regulator Architecture for Fast Transient Response

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Solution Overview

Problem

New circuits face increased power needs, requiring improved power delivery systems with enhanced control schemes.

Innovation Solution

A power delivery system is implemented with a first chip integrating a load circuit and a power delivery circuit, where the power delivery circuit includes error management and switch control circuits, with portions of the power switches on a second chip, enabling rapid voltage regulation and communication between chips for optimal power delivery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If power delivery systems use traditional single-chip integration, then device complexity is reduced, but voltage regulation precision and responsiveness to transient demands deteriorate

Engineering Contradiction:
Improvevoltage regulation precisionVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The power delivery system is divided into two separate chips: a first chip containing the load circuit and a second chip containing the power delivery circuit with error management and switch control circuits. This segmentation allows each chip to be optimized for its specific function, improving voltage regulation precision while distributing system complexity across multiple components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A communication interface acts as an intermediary between the first chip and second chip, enabling rapid exchange of voltage regulation data and control signals. This intermediary mechanism maintains tight coupling and fast response times despite the physical separation, resolving the contradiction between precision and complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If power delivery circuits are deeply integrated across multiple chips, then voltage regulation precision and transient response improve, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidmanufacturing ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By segmenting the power delivery system into specialized chips (load circuit on first chip, power delivery circuit on second chip), each component can be manufactured using optimized processes for its specific function, improving overall power delivery efficiency while making the manufacturing of individual components more manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second chip is designed to universally handle multiple power delivery functions including error management, switch control, and voltage regulation across different phases. This multi-functionality consolidates complexity into a single dedicated component, improving power delivery efficiency without proportionally increasing manufacturing difficulty.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If traditional power delivery architectures are used, then device complexity is low, but responsiveness to transient power demands and voltage regulation speed deteriorate

Engineering Contradiction:
Improvevoltage regulation speedVSAvoidcircuit architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The segmentation of control functions into a dedicated second chip with error management and switch control circuits enables faster processing of voltage regulation errors and transient demands. This architectural separation allows parallel processing of multiple phases and rapid response to load changes, improving voltage regulation speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error management circuit continuously monitors voltage deviations and provides real-time feedback to the switch control circuit, which immediately adjusts power switch timing and duty cycles. This closed-loop feedback mechanism, enabled by the dedicated second chip, achieves rapid voltage regulation response despite increased architectural complexity.

Inventive Principle:
Principle #23Feedback

4Power

If multiple phases are used for power delivery, then power delivery efficiency and transient response improve, but device complexity and control scheme complexity increase

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidcontrol scheme complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The second chip is designed as a universal power delivery controller that can manage multiple phases simultaneously through integrated error management and switch control circuits. This multi-functional design enables high power delivery capability across multiple phases while consolidating control logic into a single component, reducing the perceived complexity of the control scheme.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The multi-phase power delivery system operates with continuous switching and power transfer across all phases, maintaining constant power delivery to the load. The error management circuit continuously monitors and adjusts all phases simultaneously, ensuring uninterrupted power supply and improving overall power delivery capability without proportionally increasing control complexity.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12620901B2Deeply integrated voltage regulator architectures
Publication Date: 2026.05.05 EMPOWER SEMICONDUCTOR INC
  • US12620901B2 patent drawing
  • US12620901B2 patent drawing
  • US12620901B2 patent drawing

AI summary

A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.