Ultrahigh Voltage Charge Pump Using Low Voltage CMOS
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Solution Overview
Problem
Existing high voltage charge pump architectures, such as the Dickson charge pump, require high voltage components to achieve ultra-high voltage levels, leading to increased die area and fabrication costs, and are limited by the reverse breakdown voltage of parasitic diodes.
Innovation Solution
A charge pump architecture utilizing a cascade of NMOS stages with the bulk terminal of latter stages biased below the reverse breakdown voltage of parasitic diodes, allowing the generation of ultra-high DC voltages using standard low voltage CMOS technology, where the bias voltage is tapped from a lower voltage point within the charge pump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high voltage components are used to achieve ultra-high voltage levels, then the output voltage level is improved, but the die area and fabrication cost increase
Solution Approach 1:
The patent changes the biasing parameters of the bulk terminals in the charge pump stages. By biasing the bulk terminal of each stage to a voltage that is a fraction (e.g., 1/N) of the output voltage, the circuit can operate with standard low-voltage CMOS components while achieving ultra-high output voltages, thereby avoiding the need for high-voltage components that would increase die area.
2Strength
If high voltage components are used to achieve ultra-high voltage levels, then the output voltage level is improved, but the fabrication cost increases
Solution Approach 1:
The patent changes the operating parameters by biasing bulk terminals to fractional voltages of the output, enabling the use of standard low-voltage CMOS fabrication processes. This approach maintains ease of manufacture and lowers fabrication costs while still achieving ultra-high output voltage levels through the cascaded charge pump architecture.
3Area of stationary object
If standard low voltage CMOS technology is used, then the die area and fabrication cost are reduced, but the output voltage level is limited by the reverse breakdown voltage of parasitic diodes
Solution Approach 1:
The patent changes the bulk terminal biasing parameters from traditional ground or supply voltage to a fractional voltage (e.g., Vout/N) that scales with the output voltage. This parameter change allows each stage to operate within its safe voltage limits while the cascaded structure multiplies the effect, achieving ultra-high output voltages without exceeding the breakdown voltage of parasitic diodes in any single stage.
Solution Approach 2:
The charge pump is divided into multiple stages, each operating at a manageable voltage level. By segmenting the voltage multiplication across N stages with appropriately biased bulk terminals, the system achieves high overall output voltage while each individual stage remains within the safe operating range of standard low-voltage CMOS components.
4Strength
If the bulk terminal is biased to maximize output voltage, then the output voltage level is improved, but the reliability decreases due to approaching breakdown voltage
Solution Approach 1:
The patent optimizes the bulk terminal bias voltage to a specific parameter value (fractional voltage Vout/N) that balances two competing requirements: maximizing output voltage while maintaining a safety margin below the breakdown voltage of parasitic diodes. This parameter optimization ensures both high output voltage and reliable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of ultra-high output voltage levels without the need for high voltage technology, reducing die area and fabrication costs while exceeding the typical voltage limits of standard low voltage CMOS technology.
Implementation Method 1
each of the plurality of stages implemented with a transistor having a bulk diode with a reverse breakdown voltage, wherein one of the plurality of stages has a bulk diode at an operational voltage below the reverse breakdown voltage
Data Source
AI summary
An charge pump architecture capable of generating ultra high DC voltages but implemented in low voltage CMOS technology uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. The bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage.