Charge Pump Tail Current Chopping for PLL Noise Cancellation
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Solution Overview
Problem
Traditional PLL architectures face challenges in reducing charge pump noise while maintaining reasonable area consumption and power efficiency, as conventional methods either require excessive transistor sizing or result in uncorrelated noise sources, limiting phase noise performance and increasing power consumption.
Innovation Solution
A charge pump circuit with a sampling capacitor, voltage buffer, and discharge transistor configuration that generates both offset and down currents from a single source, using switch states to correlate noise sources and minimize noise through a chopping operation, reducing the need for large transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional approaches increase the size of tail current source transistors to reduce charge pump noise, then phase noise performance is improved, but area overhead increases substantially
Solution Approach 1:
The patent applies periodic action through tail current source chopping, where the tail current is modulated at a frequency higher than the loop bandwidth. This periodic modulation cancels low-frequency noise components (1/f noise) while maintaining the average current level, thereby improving phase noise performance without requiring larger transistor sizes and avoiding excessive area overhead.
Solution Approach 2:
The patent changes the operational parameters of the tail current source by introducing a chopping frequency parameter and modulating the current in a periodic manner. This parameter transformation converts the continuous DC current into a time-varying current with specific frequency characteristics, enabling noise cancellation through spectral shaping without increasing device dimensions.
2Object-generated harmful factors
If traditional approaches increase transistor size to reduce noise contributions, then noise performance is improved, but parasitic capacitance increases and adversely affects PLL performance
Solution Approach 1:
By implementing periodic chopping of the tail current source at a frequency above the loop bandwidth, the patent suppresses low-frequency noise without requiring large transistor sizes. This periodic modulation shifts the noise spectrum away from the critical low-frequency region, reducing both noise contributions and associated parasitic capacitance effects that would otherwise require oversized transistors to manage.
Solution Approach 2:
The patent converts the potentially harmful low-frequency noise from the tail current source into a beneficial effect by using chopping to cancel this noise. The periodic modulation transforms the harmful 1/f noise into high-frequency components that are filtered out by the loop filter, thereby turning the noise source into a mechanism for noise reduction without needing larger transistors that would introduce parasitic capacitance.
3Reliability
If traditional architectures generate signal and offset currents from separate branches, then circuit functionality is achieved, but four noise-contributing transistors result requiring significant upsizing
Solution Approach 1:
The patent merges the generation of signal current and offset current into a single tail current source that is subjected to chopping. By combining these functions into one current path with periodic modulation, the design reduces the number of independent noise-contributing transistors from four to two, while maintaining the required circuit functionality through the chopped current that provides both signal and offset components.
4Device complexity
If single-branch implementations route significant current to ground, then current sourcing is simplified, but unnecessary power consumption occurs
Solution Approach 1:
The periodic chopping of the tail current source enables precise control of current flow timing and magnitude. This periodic action allows the circuit to source current only when needed for signal generation, rather than continuously routing significant current to ground, thereby reducing unnecessary power consumption while maintaining simplified current sourcing architecture through the single chopped current path.
Data Source
AI summary
A charge pump includes an output node having a control current signal and a reference current input. The charge pump comprises a tail transistor configured to output a tail current and a DN transistor, coupled to the output node and the tail transistor responsive to a DN signal from a PFD. A voltage buffer receives the control current signal from the output node. A discharge transistor, controlled by a discharge signal, couples the sampling capacitor's bottom plate and a third switch with the tail transistor. During a first period, the sampling capacitor's top plate is connected to the buffer output through the first switch while the bottom plate supplies a discharge current to the DN transistor. During a second period, an offset current is provided to the output node and a down current is provided to the tail transistor from the top plate through a second switch and third switch.