Charge-Sharing Data Buses for Low-Power High-Speed Memory
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Solution Overview
Problem
Current memory designs face challenges in balancing data access speed and power consumption, particularly in DRAM systems where data buses consume more than 10% of total current, making it difficult to achieve high data access speed while lowering voltage levels.
Innovation Solution
The implementation of a charge share circuit that couples read/write data lines across data buses based on relative voltage levels, allowing for mid-range voltage equalization between high and low logic levels, enabling efficient data transfer while maintaining previous logic levels during charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage level applied to RWBS is lowered to reduce power consumption, then power consumption is reduced, but data access speed becomes difficult to maintain at high levels
Solution Approach 1:
The charge share circuit equalizes voltage levels between complementary data lines by sharing charge when they are at different logic levels. This allows the system to operate with reduced voltage swings while maintaining signal integrity and timing requirements, thereby reducing power consumption without sacrificing data access speed.
Solution Approach 2:
The invention changes the voltage parameter by introducing mid-range voltage levels through charge sharing. Instead of full swing between VDD and VSS, the charge share circuit creates intermediate voltage states that reduce the energy required for voltage transitions while maintaining adequate signal margins for reliable data transmission.
2Loss of energy
If voltage level applied to RWBS is lowered to reduce power consumption, then power consumption is reduced, but the ability to achieve high data access speed deteriorates
Solution Approach 1:
By equalizing voltage levels between complementary data lines through charge sharing, the system reduces unnecessary voltage swings and associated current consumption. This maintains data transfer efficiency by ensuring that voltage levels remain within acceptable margins for reliable signal detection while minimizing energy loss.
Solution Approach 2:
The invention converts what would normally be wasted charge (when complementary lines are driven to opposite rails) into a beneficial resource. The charge on one line is shared with the other, reducing overall power consumption while the controlled voltage transitions maintain data transfer integrity and speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by allowing data buses to operate at mid-range voltages, thereby optimizing data access speed and power efficiency in memory systems.
Implementation Method 1
a charge share circuit coupled between the read/write data lines. The charge share circuit is configured to share charge between the read/write data lines responsive to a charge share control signal
Data Source
AI summary
Apparatuses and methods for charge sharing across data buses based on respective levels of the data buses are disclosed herein. An example apparatus may include a first bus, a second bus, and a charge sharing circuit coupled to each of the first bus and the second bus. The charge sharing circuit may be configured to couple the first bus to the second bus based on logic levels of the first bus and the second bus. For example, the charge sharing circuit may couple the first bus to the second bus responsive to the first bus and the second bus having inverted logic levels.