Charge Storage Transistor Gate Stack With High-k Dielectric Feet
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Solution Overview
Problem
Conventional integrated circuit fabrication methods do not effectively utilize charge storage structures in transistor gates, limiting the ability to program transistors into multiple states, which is crucial for advanced memory technologies like flash memory.
Innovation Solution
The method involves forming transistor gates with charge storage structures, such as metallic nanoparticles embedded in a high-k dielectric, over a tunnel dielectric, and using a control gate structure, allowing for the storage and programming of charge, enabling multiple programming states. This is achieved through a specific sequence of material deposition and etching processes, including dry plasma etching and ion implantation, to create laterally projecting feet and selectively etching the high-k dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional integrated circuit fabrication methods are used, then manufacturing simplicity is maintained, but the ability to program transistors into multiple states is limited
Solution Approach 1:
The patent implements a nested gate structure where a control gate is positioned over a charge storage structure, which itself is positioned over a tunnel dielectric layer on the semiconductor substrate. This nested arrangement enables multi-state programming capability by allowing charge to be stored and controlled in distinct layers, thereby increasing adaptability without requiring entirely new fabrication approaches.
Solution Approach 2:
The charge storage structure is formed as a composite material system, combining a dielectric material with embedded conductive particles (such as metallic nanoparticles). This composite structure provides both the charge storage functionality needed for multi-state programming and compatibility with existing semiconductor fabrication processes, balancing versatility with manufacturing feasibility.
2Adaptability or versatility
If charge storage structures are added to transistor gates, then multi-state programming is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The charge storage structure is formed as a preliminary layer before the control gate is deposited. This sequence allows the charge storage structure to be patterned and positioned with appropriate precision using established fabrication techniques, while the subsequently deposited control gate provides additional structural support and electrical control, distributing the precision requirements across multiple fabrication steps.
Solution Approach 2:
The patent utilizes changes in material parameters, specifically employing a dielectric material with high-k (dielectric constant) properties for the charge storage structure. This parameter change enables enhanced charge storage capacity and improved control characteristics, allowing multi-state programming to be achieved with relaxed geometric precision requirements compared to conventional low-k structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of programmable charge storage transistors that can be used in advanced memory systems, such as flash memory, by effectively storing and retrieving data through charge manipulation, enhancing the functionality and efficiency of memory devices.
Implementation Method 1
The gate construction may include a control gate structure formed over charge storage structures. The charge storage structures may comprise material capable of retaining/storing/trapping charge. One example charge storage material comprises metallic nanoparticles embedded in a high-k dielectric
Implementation Method 2
The charge storage structures may be immediately adjacent a tunnel dielectric
Implementation Method 3
This is achieved through a specific sequence of material deposition and etching processes, including dry plasma etching and ion implantation
Implementation Method 4
This is achieved through a specific sequence of material deposition and etching processes, including dry plasma etching and ion implantation
Data Source
AI summary
Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.