Charge Transfer Circuit Capacity Increase via Clock Modulation
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Solution Overview
Problem
In charge-domain signal-processing circuits, increasing the signal-to-noise ratio (SNR) by enhancing capacitance alters charge transfer characteristics and results in larger, power-consuming circuits, making it necessary to find an alternative method that does not change these characteristics.
Innovation Solution
A clock signal is applied to a charge storage device, adjusting the voltage difference across a capacitor during charge transfer and then returning it to the initial condition, thereby increasing charge capacity without altering the charge transfer function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitance is increased to improve signal-to-noise ratio, then charge capacity increases, but charge transfer characteristics are altered
Solution Approach 1:
The patent applies dynamics by making the voltage difference across the capacitor time-varying through clock signal modulation. The voltage difference dynamically changes between a first value during charge transfer and a second value during reset, enabling the capacitor to achieve higher effective capacitance during signal storage while maintaining proper charge transfer characteristics during operation
Solution Approach 2:
The patent implements periodic action by using a clock signal to periodically modulate the voltage difference across the capacitor. The voltage difference alternates between the first value and second value in periodic cycles, allowing the capacitor to accumulate more charge over each cycle while preserving the original charge transfer function during the active phase
2Reliability
If capacitance is increased to improve signal-to-noise ratio, then charge capacity increases, but circuit size and power consumption increase
Solution Approach 1:
The patent applies parameter changes by modifying the voltage difference parameter across the capacitor rather than changing the physical capacitance value. By changing the voltage parameter dynamically through clock signal control, the effective charge capacity increases without requiring larger physical capacitors, thus avoiding increased power consumption and circuit size
3Quantity of substance
If voltage difference across capacitor is adjusted during charge transfer, then charge capacity increases, but charge transfer characteristics may be altered
Solution Approach 1:
The patent applies segmentation by dividing the capacitor operation into distinct time segments or phases. During the charge transfer phase, the voltage difference is maintained at the first value to preserve transfer characteristics. During the reset phase, the voltage difference switches to the second value to enable additional charge capacity. This temporal segmentation allows both requirements to coexist
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles the charge capacity of the circuit without changing the charge transfer characteristics, avoiding the drawbacks of increased capacitance, such as larger size and higher power consumption.
Implementation Method 1
the capacitance on which the charge packet is stored, in Farads
Implementation Method 2
A clock signal is applied to a charge storage device, adjusting the voltage difference across a capacitor during charge transfer
Data Source
Figure 1~2
Figure 3~4B
Figure 5
AI summary
A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.