Charge-Trap Flash Memory Erase Biasing for Parasitic Effect Reduction
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Solution Overview
Problem
Parasitic effects in NAND FLASH memory devices, such as electron trapping in isolation oxides, lead to incorrect data reading and irreversible damage, limiting memory array density and alternative geometries.
Innovation Solution
Applying specific bias voltages to selector and memory transistors during an erase operation to reduce electric field strength and prevent electron tunneling into isolation oxides, thereby managing threshold voltages and reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array density is increased to meet consumer demand for larger storage capacity, then storage capacity is improved, but parasitic effects such as electron trapping in isolation oxides emerge, leading to incorrect data reading and limiting further density increases
Solution Approach 1:
The patent applies preliminary anti-action by programming selector transistors before performing the erase operation on memory cells. This preliminary programming establishes appropriate threshold voltages in selector transistors that prevent parasitic electron tunneling into isolation oxides during the subsequent erase operation, thereby preventing the harmful effect before it can occur and enabling high-density memory arrays to operate reliably
2Ease of operation
If conventional erase operation is performed with floating gates on selectors, then erase operation is simple, but gates capacitively couple to high voltage bias on p-well, causing voltage differentials that tunnel electrons into isolation oxides and create irreversible damage
Solution Approach 1:
The patent applies preliminary action by programming the selector transistors before executing the erase operation on memory cells. This preliminary programming action sets the selector transistor threshold voltages to appropriate levels, which then prevent the harmful capacitive coupling and electron tunneling that would otherwise occur during the erase operation when gates are left floating
Solution Approach 2:
The patent converts the potentially harmful effect of voltage differentials during erase operations into a beneficial outcome. By programming selector transistors beforehand, the voltage differentials that would normally cause electron tunneling into isolation oxides are transformed into controlled conditions that enable successful erasure of memory cells without damaging parasitic effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable reading, erasing, and programming of memory cells while increasing memory array density and improving cycling endurance by minimizing parasitic effects and maintaining accurate data retrieval.
Implementation Method 1
p-well 102 is biased at a high voltage, thereby creating a voltage differential across the oxide of the memory cells that is large enough to tunnel stored electrons from the charge-trap regions within the memory cells to p-well 102
Implementation Method 2
voltage differentials between gates of the selectors and gates of memory cells adjacent to the selectors can be sufficient to tunnel electrons into isolation oxides associated with memory cells adjacent to the selectors
Data Source
AI summary
FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.