Charge-Trap Island Isolation in 3D NAND Memory Cells
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Solution Overview
Problem
In 3D NAND memory devices, the close spacing of memory cells leads to charge leakage and fringing effects, compromising data storage due to the thinness of insulator layers and the proximity of charge trap regions in adjacent cells.
Innovation Solution
The formation of isolated charge trap regions, either through a 'gate-last' or 'gate-first' fabrication process, where each memory cell has a separate charge trap island, electrically and physically separated from adjacent cells by dielectric structures or air gaps, preventing electron hopping and fringing effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of insulator layers is scaled down to minimize aspect ratio, then manufacturing issues are avoided, but charge leakage between adjacent memory cells occurs
Solution Approach 1:
The patent divides the continuous charge trap layer into separate, isolated charge trap regions for each memory cell. These regions are physically separated by removing portions of the charge trap layer between adjacent cells, preventing charge leakage while allowing thin insulator layers to be used.
Solution Approach 2:
The patent extracts or removes portions of the charge trap layer that would otherwise create leakage paths between adjacent memory cells. By taking out these intermediate portions, isolated charge trap regions are formed that cannot exchange charges with neighboring cells.
2Quantity of substance
If memory cells are closely spaced to increase density, then storage capacity increases, but fringing effects affect charge in neighboring cells
Solution Approach 1:
The patent segments the charge trap layer into discrete, isolated regions for each memory cell. This segmentation creates electrical isolation between closely spaced cells, eliminating fringing effects that would otherwise allow electric fields from one cell to affect charge in neighboring cells.
3Device complexity
If a continuous charge trap layer is used to simplify fabrication, then manufacturing complexity is reduced, but charge leakage between cells compromises data integrity
Solution Approach 1:
The patent performs preliminary action by forming the continuous charge trap layer first, then selectively removing portions between cells in a subsequent step. This approach maintains fabrication simplicity while achieving the necessary charge isolation for data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that charge trap regions are not susceptible to leakage, maintaining data integrity even when insulator layers are thin, and provides effective word-line isolation, enhancing the reliability of 3D NAND memory cells.
Implementation Method 1
depositing a charge trap layer on inner surfaces of the memory hole to form a charge trap region for each memory cell
Implementation Method 2
performing an etch process on the edge surface of each layer to selectively remove a portion of each memory cell layer and form first cavities
Implementation Method 3
oxidizing the exposed portion of each memory cell layer so that an oxide region is formed between insulator layers
Data Source
AI summary
In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.