Charge Trap Layer Between Word Line and Active Region
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Solution Overview
Problem
The height of the floating gate in flash memory devices acts as an impediment to further scaling down the size of highly integrated flash memory devices, necessitating the development of alternative non-volatile semiconductor memory solutions that enhance reliability and performance.
Innovation Solution
Non-volatile semiconductor memory devices are designed with a word line having a reverse-arch recess, an active region within the recess, and charge trap layers between the word line and active region, along with dielectric and tunnel insulating layers, forming a SONOS structure to improve data storage efficiency and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating gate structure is used in flash memory devices, then data storage capability is improved, but device scaling is hindered due to the height of the floating gate
Solution Approach 1:
The patent extracts the charge storage function from the traditional floating gate structure and relocates it to a separate charge trap layer positioned between the control gate and the active region. This separation allows the control gate to be flattened, enabling device scaling while preserving data storage capability in the charge trap layer.
Solution Approach 2:
The patent transitions from a vertical stacked floating gate structure to a lateral charge trap configuration. By positioning the charge trap layer horizontally between the control gate and active region rather than stacking it vertically, the device achieves scaling in the vertical dimension while maintaining storage function in the lateral dimension.
2Ease of manufacture
If conventional memory structures are used, then manufacturing process is simpler, but short channel effects increase and reliability decreases
Solution Approach 1:
The patent applies local quality by introducing the charge trap layer specifically at the interface region between the control gate and active region, where electric field concentration occurs. This localized charge storage mechanism provides better control over short channel effects in the critical region without complicating the overall manufacturing process.
Solution Approach 2:
The patent employs a composite structure consisting of multiple functional layers: control gate, dielectric layer, charge trap layer, and tunnel insulating layer. This composite architecture combines the advantages of each material layer to achieve both ease of manufacture using standard semiconductor processes and improved reliability through enhanced electric field control.
3Loss of energy
If charge trap layers are introduced between word lines and active regions, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the control gate and charge trap layer, and a tunnel insulating layer as an intermediary between the charge trap layer and active region. These intermediary layers reduce parasitic capacitance by providing electrical isolation while maintaining the necessary functional coupling, and they can be integrated using standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data program/erase operations, reduces parasitic capacitance and power consumption, and allows for more efficient scaling of memory devices by increasing the width of the channel region and strengthening the electric field within the tunnel insulating layer.
Implementation Method 1
a tunnel insulating layer may be disposed between the active region and the charge trap layer
Implementation Method 2
A charge trap layer is disposed between the word line and the active region
Implementation Method 3
a dielectric layer may be disposed between the charge trap layer and the word line
Data Source
AI summary
A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.