Charge Trap Structures With Voids For 3D Memory Scaling
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Solution Overview
Problem
The electronics industry faces challenges in reducing component size and power requirements in memory devices, particularly in three-dimensional (3D) configurations, where existing charge trap memory devices struggle with efficient operation and scaling due to coupling issues between charge trap regions and access lines.
Innovation Solution
The implementation of a charge trap structure with a dielectric barrier and voids between charge trap regions, allowing for vertical scaling and reduced coupling, which includes forming a dielectric barrier between the dielectric blocking region and the gate, and creating voids to separate charge trap regions, enabling enhanced control over capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If charge trap regions are placed closer together to reduce tier pitch, then memory density increases, but coupling between charge trap regions increases causing charge hopping
Solution Approach 1:
The patent introduces voids that segment the charge trap structures into isolated regions. These voids act as physical barriers that divide the continuous charge trap region into discrete segments, preventing charge hopping between adjacent charge trap regions while maintaining high density through vertical stacking.
Solution Approach 2:
The voids serve as intermediary elements between adjacent charge trap regions. By introducing these intermediate void spaces, the patent prevents direct coupling between charge trap regions, thereby eliminating charge hopping while allowing the charge trap structures to be positioned close together for high density.
2Length of moving object
If tier pitch is reduced from 65 nm to 30 nm, then memory device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The voids are formed preliminarily during the fabrication process before final charge trap region formation. By pre-establishing the void structures as spacers or templates, the patent simplifies subsequent processing steps and reduces the precision requirements for later alignment-critical steps, enabling successful fabrication at 30 nm tier pitch.
3Object-generated harmful factors
If voids are introduced to separate charge trap regions, then coupling is minimized, but device complexity increases
Solution Approach 1:
The patent merges the void formation process with existing fabrication steps, such as combining void formation with spacer formation or integrating void creation into the tunnel oxide formation sequence. By merging multiple functions into unified process steps, the patent reduces overall device complexity despite the addition of void structures.
Data Source
AI summary
Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.