Charge Trapping Memory Structure With Divots for ONO Etch Control
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Solution Overview
Problem
The existing oxide-nitride-oxide (ONO) structure in semiconductor memory devices faces issues with over-etching during the etching process, leading to high-k residue encroachment in the trench isolation region, which affects the device's reliability and performance.
Innovation Solution
A method is developed to form a semiconductor memory device with a charge trapping structure comprising a bottom oxide layer, a nitride layer, and a top oxide layer, where divots are created in the trench isolation region to prevent high-k residue encroachment, and a silicon oxide layer is formed in these divots, ensuring precise control over the etching process and reducing over-etching risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is used to define the ONO structure profile, then the memory cell profile is precisely defined, but over-etching occurs in the trench isolation region leading to high-k residue encroachment
Solution Approach 1:
A buffer oxide layer is formed on the trench isolation region before the main etching process. This buffer layer serves as a protective barrier that prevents the etching process from penetrating into the trench isolation region, thereby preventing over-etching and high-k residue encroachment while allowing the ONO structure profile to be precisely defined in the active area
Solution Approach 2:
The buffer oxide layer is selectively formed only on the trench isolation region, creating a local protective barrier. This allows the etching process to proceed normally in the active area for precise ONO structure definition while being blocked in the trench isolation region, thus resolving the contradiction between profile precision and isolation region integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication process by preventing high-k residue encroachment and improving the reliability of the semiconductor memory device, ensuring accurate profile definition and reduced risk of over-etching, thereby enhancing device performance and stability.
Implementation Method 1
An oxidation process is performed to form a gate oxide layer on the at least one active area around the charge trapping structure and a silicon oxide layer in the at least one divot
Data Source
AI summary
A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.