Charge Trapping Layer Extension for Narrow Channel NAND Flash
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Solution Overview
Problem
NAND flash memory devices with self-aligned shallow trench isolation (STI) and a channel width less than 50 nm fail to program properly due to edge fringing field effects, as the charge storage layer does not extend beyond the source/drain region, leading to functional limitations.
Innovation Solution
Extending the charge trapping layer, such as a nitride layer, beyond the source/drain region and into the shallow trench, allowing it to wrap around the polysilicon corners, effectively shutting off the corner region and improving programming capabilities by increasing the separation between programmed and unprogrammed states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel width is reduced to increase storage density, then storage capacity increases, but programming reliability deteriorates due to edge fringing field effects
Solution Approach 1:
The charge storage layer is extended locally beyond the source/drain region into the shallow trench isolation region. This creates a non-uniform structure where the charge storage capability is enhanced at the critical edge regions where fringing fields occur, while maintaining the original channel structure. The extended portion specifically addresses the local field concentration problem without requiring global structural changes.
Solution Approach 2:
The charge storage layer is extended in the lateral dimension beyond the conventional source/drain region boundaries into the STI region. This dimensional extension creates an additional charge storage zone that compensates for the fringing field effects, effectively adding a new spatial dimension to the charge storage function to improve programming reliability in narrow channel devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables proper programming of narrow NAND flash memory devices by isolating the edge fringing fields, distinguishing between programmed and unprogrammed states, and enhancing the device's programming efficiency.
Implementation Method 1
NAND flash memory devices with self-aligned shallow trench isolation (STI) and a channel width less than 50 nm do not program properly due to edge fringing field effects
Data Source
AI summary
A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.