Charge-Trapping Memory Cell Layout for 1.5T Program-Erase Operation
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Solution Overview
Problem
Conventional charge-trapping non-volatile memory cells require two transistors for programming and erasing, which complicates the structure and efficiency of data storage.
Innovation Solution
A memory cell design featuring a semiconductor substrate with a well region, doped regions, a gate structure, a protecting layer, a charge trapping layer, and conducting lines, where the protecting layer is made of oxide and serves as a salicide block or resist protect oxide layer, allowing for a 1.5 T cell configuration with an oxide/nitride/oxide storage structure that enables efficient programming and erasing through controlled carrier injection and recombination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two complete transistors are used for programming and erasing, then reliable data storage is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the charge trapping function from a complete transistor structure and implements it using only the essential components (gate structure, trapping layer, and one doped region), eliminating redundant parts while maintaining the core functionality of data storage and retrieval
Solution Approach 2:
The gate structure serves multiple functions: it controls carrier injection into the trapping layer during programming, enables carrier extraction during erasing, and acts as the control electrode for the 1.5T cell operation, replacing what would traditionally require separate control mechanisms in a 2T cell
2Ease of manufacture
If two complete transistors are used for programming and erasing, then data storage functionality is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the programming and erasing functionalities into a single integrated structure where the gate structure and trapping layer work together as a unified storage element, reducing the number of discrete components that need to be fabricated and assembled
Solution Approach 2:
The memory cell is segmented into functional regions (well region, doped regions, gate structure, trapping layer) that can be independently formed through sequential processing steps, allowing for modular manufacturing and simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the memory cell structure, enhances programming and erasing efficiency, and allows for reliable storage state transitions by utilizing a 1.5 T cell configuration with an oxide/nitride/oxide storage structure, improving operational voltages and reducing complexity.
Implementation Method 1
charges (e.g., electrons) are transmitted from the channel region of the storage transistor Ms to the trapping layer 124 through the tunneling layer 122
Implementation Method 2
in case that charges are stored in the trapping layer 124 of the storage transistor Ms, the memory cell is in a second storage state
Implementation Method 3
enables efficient programming and erasing through controlled carrier injection and recombination
Data Source
AI summary
A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.