Charge Trapping Memory Cell with High-k Blocking Dielectric for Fast Erase
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Solution Overview
Problem
Existing flash memory technologies face challenges in increasing density due to cell-to-cell interference in floating gate memory cells and suffer from poor endurance and charge retention in charge trapping memory cells, particularly with thin tunneling dielectric layers, which limits erase speed and causes saturation issues.
Innovation Solution
A blocking dielectric engineered charge trapping memory cell using a metal doped silicon oxide with a dielectric constant greater than silicon dioxide, paired with a bandgap engineered tunneling dielectric, allowing for fast programming and erasing without saturation, while maintaining excellent reliability and retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the tunneling dielectric layer is made thin (less than 30 Å) to achieve fast erase speed, then erase speed is improved, but charge retention and endurance deteriorate
Solution Approach 1:
The patent changes the dielectric constant parameter of the blocking dielectric layer from conventional silicon oxide (κ≈3.9) to high-k materials such as aluminum oxide (κ≈9-10), hafnium oxide (κ≈20-25), or tantalum oxide (κ≈25-30). This parameter change allows the blocking dielectric to better confine electrons under high electric fields during erase operations, enabling fast erase speeds while maintaining charge retention and endurance even with thin tunneling dielectric layers.
Solution Approach 2:
The patent employs a composite dielectric stack consisting of a tunneling dielectric layer (such as silicon oxide) combined with a high-k blocking dielectric layer (such as aluminum oxide, hafnium oxide, or tantalum oxide). This composite structure leverages the beneficial properties of each material: the tunneling dielectric enables charge injection/extraction while the high-k blocking dielectric provides superior electron confinement, resolving the contradiction between fast erase speed and reliable charge retention.
2Reliability
If a thick tunneling dielectric layer is used to maintain good charge retention, then charge retention is improved, but erase speed deteriorates due to insufficient electric field for hole tunneling
Solution Approach 1:
The patent increases the dielectric constant parameter of the blocking dielectric layer to high-k materials (κ≥9), which enhances the material's ability to sustain high electric fields. This allows the use of thicker tunneling dielectric layers that provide good charge retention while the high-k blocking dielectric maintains sufficient electric field strength for rapid hole tunneling during erase operations.
3Speed
If high electric field is applied to achieve fast erase, then erase speed is improved, but electron injection from gate through blocking dielectric increases causing erase saturation
Solution Approach 1:
The patent changes the dielectric constant of the blocking dielectric layer to a high-k material (κ≥9), which reduces the electric field magnitude required to achieve the same displacement field strength. This allows fast erase operations to be performed at lower applied voltages, preventing excessive electron injection through the blocking dielectric and avoiding erase saturation while maintaining high erase speeds.
Solution Approach 2:
The patent converts the potentially harmful effect of high electric fields (which cause electron injection through the blocking dielectric) into a beneficial outcome by using high-k blocking dielectric materials. These materials enable the system to achieve the necessary electric displacement field for fast erase at lower applied voltages, thereby eliminating the harmful electron injection while preserving the benefit of fast erase speed.
4Ease of manufacture
If silicon oxide blocking dielectric is used, then manufacturing simplicity is maintained, but electron injection through the blocking dielectric increases during high field erase operations
Solution Approach 1:
The patent replaces the conventional silicon oxide blocking dielectric with high-k dielectric materials such as aluminum oxide, hafnium oxide, or tantalum oxide. These materials provide superior electron confinement properties during high field erase operations, significantly reducing electron injection through the blocking dielectric while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent changes the dielectric constant parameter of the blocking dielectric from κ≈3.9 (silicon oxide) to κ≥9 (high-k materials), which fundamentally improves the material's ability to confine electrons under high electric fields. This parameter change reduces electron injection during erase operations while the materials remain compatible with existing manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed erase operations without saturation, improves memory window size, and enhances charge retention and endurance, making it suitable for small-scale memory devices with reduced manufacturing complexity.
Implementation Method 1
the electric field required for the erase operation also cause electron injection from the gate through the blocking dielectric layer
Implementation Method 2
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunnel dielectric layer
Implementation Method 3
the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O)
Data Source
AI summary
A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.