Charge Trapping Memory With Multi-Layer Tunneling Structure
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Solution Overview
Problem
Charge trapping memory technologies face challenges with erase saturation and poor endurance due to high electric fields required for erase operations, which affect the operational speed and reliability, especially as device sizes shrink.
Innovation Solution
A charge trapping memory cell design with a multi-layer tunneling structure and multiple nitride layers is introduced, where the control circuit applies specific bias arrangements to program and erase data, utilizing the tunneling valence band edge and electron density in nitride layers to prevent erase saturation and enhance charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin tunneling dielectric layer is used to achieve fast erase operation, then erase speed is improved, but charge retention and endurance deteriorate
Solution Approach 1:
The patent divides the single charge storage layer into multiple charge storage layers (first charge storage layer and second charge storage layer) separated by a blocking dielectric layer. This segmentation allows independent management of charge storage functions, enabling fast erase operation in one layer while maintaining charge retention in another layer, thus resolving the contradiction between erase speed and charge retention.
2Reliability
If a thick tunneling dielectric layer is used to improve charge retention, then charge retention is improved, but erase speed deteriorates
Solution Approach 1:
The patent segments the charge storage function across multiple layers with different thicknesses. The first charge storage layer can be thinner for fast erase, while the second charge storage layer can be thicker for better charge retention, eliminating the need to compromise either parameter.
3Speed
If high electric field is applied to achieve fast erase, then erase speed is improved, but electron injection from gate increases causing erase saturation
Solution Approach 1:
The patent introduces a blocking dielectric layer as an intermediary between the two charge storage layers. This blocking layer prevents electron injection from the gate from reaching the first charge storage layer, thereby eliminating erase saturation while allowing fast erase operation to proceed in the second charge storage layer.
Solution Approach 2:
The patent segments the charge storage layers into two distinct layers with different functions. The first charge storage layer handles fast erase operations, while the second charge storage layer maintains charge retention, preventing the harmful effects of electron injection from compromising overall device performance.
4Use of energy by moving object
If high-K dielectric material is used to reduce operating voltage, then power consumption is reduced, but data retention deteriorates due to shallow traps
Solution Approach 1:
The patent employs composite dielectric structures combining different materials (oxide and nitride layers) with different properties. The oxide layers provide low leakage for good data retention, while the nitride layers provide high breakdown field for reduced operating voltage, thus achieving both low power consumption and reliable data retention through material composition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents erase saturation and improves charge retention by controlling electron and hole injection, allowing for faster and more reliable programming and erasing without compromising data integrity, even at higher gate voltages.
Implementation Method 1
The tunneling dielectric layer must be quite thin (less than 30 Å)... electron tunneling using one of a number of well-known biasing technologies
Implementation Method 2
the blocking dielectric layer is formed a silicon oxide (O)... the electric field required for the erase operation also cause electron injection from the gate through the blocking dielectric layer
Implementation Method 3
Charge trapping memory is a class of non-volatile integrated circuit memory technology which stores data by employing dielectric charge trapping material to store charge
Data Source
AI summary
A memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack comprises a multi-layer tunneling structure on the channel surface, a first charge storage nitride layer on the multi-layer tunneling structure, a first blocking oxide layer on the first charge storage nitride layer, a second charge storage nitride layer on the first blocking dielectric layer, and a second blocking oxide layer on the second charge storage nitride layer. The multi-layer tunneling structure includes a first tunneling oxide layer, a first tunneling nitride layer on the first tunneling oxide layer, and a second tunneling oxide layer on the first tunneling nitride layer.