Charged Dielectric Interconnect Structure Against Grinding Cracks
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Solution Overview
Problem
Integrated chips face reliability issues due to dielectric layers cracking under downward forces during grinding processes, leading to reduced time-dependent dielectric breakdown and increased electromigration, which compromises the overall chip reliability.
Innovation Solution
Incorporating charged dielectric layers with the same polarity on opposite sides of a dielectric layer to create an electrostatic force that counteracts the downward force, thereby reducing the likelihood of cracking and enhancing the reliability of the dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If downward force is applied during grinding to thin the substrate, then substrate thickness is reduced, but dielectric layers are damaged causing cracking
Solution Approach 1:
The patent applies electrostatic repulsion force between charged dielectric layers to counteract the downward mechanical force during grinding. By charging dielectric layers with the same polarity, an upward electrostatic force is generated that opposes the downward grinding force, preventing dielectric layer cracking while allowing substrate thinning to proceed.
Solution Approach 2:
The dielectric layers are pre-charged with the same polarity before the grinding process begins. This preliminary electrostatic charging creates a repulsive force that anticipates and counteracts the damaging effect of the upcoming downward grinding force, protecting the dielectric layers from cracking before the damage can occur.
2Speed
If low-k or extra low-k dielectric layers are used to reduce signal delay, then signal transmission speed is improved, but the dielectric layers become more susceptible to cracking during grinding
Solution Approach 1:
The electrostatic repulsion force generated by charging low-k or extra low-k dielectric layers with the same polarity counteracts the downward grinding force. This compensates for the reduced mechanical strength of these low-k materials, allowing them to be used for high-speed signal transmission without suffering from cracking susceptibility during the grinding process.
Solution Approach 2:
The patent changes the electrical parameter of the dielectric layers by introducing fixed charges with the same polarity. This parameter change creates an electrostatic field that modifies the mechanical behavior of the dielectric layers during grinding, providing protective repulsion force that compensates for their inherent brittleness and cracking susceptibility.
3Reliability
If charged dielectric layers are added to protect against cracking, then dielectric layer reliability is improved, but device complexity increases
Solution Approach 1:
The charged dielectric layers serve multiple functions: they provide electrical isolation between conductive interconnects (traditional dielectric function) and simultaneously generate electrostatic repulsion force to protect against cracking during grinding (protective function). This multi-functionality reduces the need for additional separate protective layers, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent modifies the electrical parameters of existing dielectric layers by introducing fixed charges, rather than adding entirely new structural elements. This parameter change approach allows the same dielectric layers to provide both their traditional isolation function and the new protective function, minimizing the increase in device complexity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The electrostatic force between the charged dielectric layers effectively counters the downward force, reducing the susceptibility of dielectric layers to cracking and improving the overall reliability of the integrated chip.
Implementation Method 1
Incorporating a pair of charged dielectric layers with the same polarity on opposite sides of a dielectric layer to create an electrostatic force that counteracts the downward force applied during grinding
Data Source
AI summary
The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.