Checkerboard Dummy Epitaxial Layout for Mixed-Voltage Chip Growth

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Solution Overview

Problem

Integrated chip structures with low voltage transistor devices operating alongside medium and high voltage devices face performance and reliability issues due to low epitaxial pattern density, leading to poor epitaxial growth and increased surface area occupancy by low voltage devices.

Innovation Solution

Incorporating dummy epitaxial regions within the integrated chip structure to increase the overall epitaxial pattern density above 5.2%, thereby improving the health of the epitaxial growth process and enhancing the performance and reliability of low voltage transistor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If low voltage transistor devices are coupled together with medium and high voltage devices on the same integrated chip structure, then device functionality is improved, but epitaxial pattern density decreases leading to poor epitaxial growth

Engineering Contradiction:

Improvedevice functionalityVSAvoidepitaxial growth quality

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Dummy epitaxial regions are formed in advance within the integrated chip structure before actual device operation. These dummy regions pre-establish the required epitaxial pattern density threshold (greater than 5.2%) to ensure healthy epitaxial growth conditions for low voltage transistor devices, preventing growth defects before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the epitaxial pattern density parameter by introducing dummy epitaxial regions. This increases the overall epitaxial pattern density from below the threshold to above 5.2%, fundamentally altering the growth conditions to enable reliable epitaxial formation in mixed-voltage integrated structures.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If low voltage transistor devices occupy increased surface area to improve performance, then device performance is enhanced, but chip area occupancy increases

Engineering Contradiction:

Improvedevice performanceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Dummy epitaxial regions are strategically placed in specific locations within the integrated chip structure where they provide localized epitaxial pattern density enhancement. This allows low voltage transistor devices to achieve reliable performance in specific regions without requiring uniform expansion across the entire chip area.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20240379664A1Checkerboard dummy design for epitaxial open ratio

Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.