Checkerboard Carry Save Multiplier Using Majority-Minority Gate Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiplier cells in CMOS logic require a large number of transistors, leading to increased power consumption and area, which poses challenges for reducing power consumption in devices.
Innovation Solution
The use of ferroelectric or paraelectric materials in logic gates, such as majority or minority gates, to create a hybrid of these gates with CMOS based inverters and buffers, resulting in a more compact and power-efficient multiplier cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional CMOS logic gates (AND, OR, XOR) are used in multiplier cells, then the circuit can perform multiplication operations, but the number of transistors increases, leading to increased power consumption and area
Solution Approach 1:
The patent changes the fundamental operating parameter of logic gates from traditional CMOS switching operations to majority/minority gate operations with non-linear capacitive elements. This parameter change enables the circuit to perform the same logical functions (AND, OR, XOR) with fewer transistors, directly resolving the contradiction between power consumption and device complexity
Solution Approach 2:
The patent employs a hybrid architecture combining majority/minority gates with non-linear polar materials (ferroelectric or paraelectric) and CMOS-based inverters/buffers. This composite approach leverages the advantages of both technologies: the reduced transistor count of majority/minority gates and the成熟 reliability of CMOS, achieving lower power consumption without sacrificing circuit functionality
2Area of stationary object
If traditional CMOS logic gates are used in multiplier cells, then the circuit can perform multiplication operations, but the area occupied by the circuit increases
Solution Approach 1:
By changing the logic gate implementation from traditional CMOS to majority/minority gates with non-linear capacitive elements, the patent reduces the transistor count required for each logical operation. This parameter change directly reduces the circuit footprint while maintaining multiplication functionality
Solution Approach 2:
The patent merges the functionality of multiple transistors into a single majority or minority gate unit. By combining the logical operations that traditionally required separate AND, OR, and XOR gates into unified majority/minority gate structures, the overall circuit area is reduced
3Power
If the circuit operates continuously to maintain functionality, then the multiplication operations can be performed without interruption, but power consumption increases during idle periods
Solution Approach 1:
The patent exploits the phase transition properties of ferroelectric or paraelectric materials in the non-linear capacitive elements. These materials can maintain their polarization state (and thus the circuit state) without continuous power supply, enabling the circuit to enter a low-power idle state while maintaining operational readiness. When power is reapplied, the circuit can quickly transition back to full operation
Solution Approach 2:
The patent enables intermittent operation where the circuit can be powered down during idle periods and activated only when multiplication operations are needed. The non-linear polar materials retain their state information, allowing the circuit to resume operation without full re-initialization,从而实现 periodic operation with zero power drain during idle time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of transistors and interconnects, leading to lower power consumption and smaller footprint, while also allowing for intermittent operation with zero power drain when not in use.
Implementation Method 1
The use of ferroelectric or paraelectric materials in logic gates, such as majority or minority gates
Implementation Method 2
The use of ferroelectric or paraelectric materials in logic gates, such as majority or minority gates
Data Source
AI summary
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.