3D Semiconductor Package Alignment Inspection for Reliable Chip Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high integration of semiconductor devices poses challenges in maintaining electrical and mechanical reliability of connection structures between multiple semiconductor chips, particularly in 3-dimensional semiconductor packages using through silicon vias, due to issues like decreased process margins and alignment accuracy.
Innovation Solution
A semiconductor package design incorporating first and second semiconductor chips with bonding pads and passivation layers, along with alignment inspection structures that include inspection electrodes and pads, allowing for precise alignment and electrical/optical inspection to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to achieve high integration, then the integration density increases, but the alignment accuracy and electrical reliability of connection structures deteriorate
Solution Approach 1:
Alignment inspection structures (inspection pads and inspection electrodes) are formed on the semiconductor chips before the stacking process. These structures serve as reference markers that enable precise alignment verification between chips during the bonding process, preventing misalignment issues that would otherwise occur in high-density stacked configurations
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with electrical field-based inspection. Inspection electrodes generate electrical fields that interact with corresponding structures on adjacent chips, enabling non-contact alignment verification and improving both alignment accuracy and electrical reliability of connection structures
2Productivity
If through silicon vias are used to form vertical electrical connections, then the electrical connection efficiency improves, but the mechanical reliability of the connection structure deteriorates
Solution Approach 1:
The patent employs composite material structures in the connection architecture, combining through silicon vias with additional bonding pads and passivation layers. This composite approach creates a multi-layered connection structure that maintains the electrical efficiency of TSVs while adding mechanical strength and reliability through the integrated bonding structures
Solution Approach 2:
The connection structure is segmented into distinct functional components: through silicon vias for electrical conduction, bonding pads for mechanical attachment, and passivation layers for structural support. This segmentation allows each component to optimize its specific function while collectively improving both electrical efficiency and mechanical reliability
3Manufacturing precision
If alignment inspection structures are added to ensure precise alignment, then the alignment accuracy improves, but the device complexity increases
Solution Approach 1:
The alignment inspection structures serve multiple functions: they provide alignment reference markers, enable electrical field-based verification, and integrate with the existing bonding pad structures. This multi-functionality reduces the need for separate dedicated alignment features, thereby limiting the increase in device complexity while maintaining improved alignment accuracy
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first wiring structure including a first wiring pattern and a first wiring insulating film, a second semiconductor chip including a second semiconductor substrate and a second wiring structure including a second wiring pattern and a second wiring insulating film, a first bonding pad on the first wiring structure, a first passivation layer surrounding a side surface of the first bonding pad, a second bonding pad electrically connected to the first bonding pad, a second passivation layer surrounding a side surface of the second bonding pad, a first alignment inspection structure horizontally apart from the first wiring pattern and penetrating the first passivation layer, and a second alignment inspection structure vertically penetrating the second semiconductor substrate, the second wiring insulating film, and the second passivation layer.