Chip Arrangement Manufacturing via Low-Temperature Bonding
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Solution Overview
Problem
Conventional methods for manufacturing chip arrangements face issues such as high bonding temperatures leading to warpage, residual stress, and the formation of copper silicides, along with complex layup structures and high material costs, due to the use of thick copper leadframes and high-temperature bonding processes.
Innovation Solution
A method involving placing a chip on a carrier within an opening of a metal structure, fixing it, and forming an electrically conductive connection between the chip and the metal structure at lower temperatures, using a simpler layup process with fewer materials and avoiding the need for complex leadframe structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-temperature bonding processes are used to attach chips to thick copper leadframes, then strong electrical and thermal connections are achieved, but warpage and residual stress occur in the chip arrangement
Solution Approach 1:
The patent extracts the carrier substrate from the final product structure, using it only as a temporary support during manufacturing. The carrier is removed after chip placement, eliminating the source of thermal expansion mismatch and warpage while maintaining bonding strength through alternative low-temperature bonding methods.
Solution Approach 2:
The patent changes the bonding temperature parameter from high temperature (conventional) to low temperature (innovative), which prevents warpage and residual stress while achieving sufficient bonding strength through optimized low-temperature bonding processes and materials.
2Reliability
If thick copper leadframes are used for chip arrangements, then electrical and thermal connections are improved, but material costs and device complexity increase
Solution Approach 1:
The patent extracts the traditional thick copper leadframe structure and replaces it with a simplified metal structure integrated directly into the carrier substrate. This eliminates unnecessary material while maintaining electrical connection reliability through optimized metal layer design.
Solution Approach 2:
The patent makes the carrier substrate multi-functional by integrating both structural support and electrical connection functions into a single component, eliminating the need for separate thick copper leadframes and reducing overall device complexity.
3Strength
If conventional high-temperature bonding processes are used, then chips are securely attached to the leadframe, but copper silicides form and material costs increase
Solution Approach 1:
The patent changes the bonding temperature parameter from high to low, which prevents copper silicide formation while achieving secure chip attachment through optimized low-temperature bonding processes and materials that do not require high thermal energy.
Solution Approach 2:
The patent uses a disposable carrier substrate that simplifies the manufacturing process and eliminates the need for expensive thick copper leadframes. The carrier is removed after serving its temporary purpose, reducing material costs while maintaining attachment strength during the bonding process.
Data Source
AI summary
A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.