Chip Backside Metallization With Embedded Metal to Limit Wafer Warping
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Solution Overview
Problem
The challenge in chip metallization is to increase the thickness of the metal layer on a chip substrate while minimizing the impact of the dielectric layer thickness, which can cause warping and difficulty in subsequent processes due to excessive thin film stress.
Innovation Solution
A chip metallization method involving etching the back surface of the chip substrate and embedding dielectric and metal thin films directly into the substrate, allowing flexible control of the metal layer thickness and reducing the dielectric layer thickness, thereby improving power supply and heat dissipation capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the dielectric layer is increased to accommodate a thicker metal layer, then the metal layer thickness can be increased, but the wafer warps due to large thin film stress
Solution Approach 1:
Instead of depositing a thick dielectric layer and then embedding the metal layer within it (conventional approach), this patent inverts the sequence by first creating recesses in the dielectric layer and then filling them with the metal layer. This allows the metal layer to be thicker without requiring a correspondingly thick dielectric layer, thus avoiding wafer warping while achieving the desired metal thickness for improved power supply capability.
Solution Approach 2:
The dielectric layer is segmented into regions with recesses (trenches) that are filled with metal. This segmentation allows the metal layer to be concentrated in specific areas where it is needed for power supply, while the overall dielectric layer thickness can be reduced, minimizing thin film stress and preventing wafer warping.
2Power
If the thickness of the metal layer is increased to improve power supply capability, then the power supply performance improves, but the dielectric layer thickness must also be increased which causes manufacturing difficulty
Solution Approach 1:
The conventional sequence of depositing dielectric material first and then metal material is inverted. The patent deposits dielectric material to form a relatively thin layer, creates recesses in this layer, and then fills the recesses with metal material. This allows achieving thick metal layers for improved power supply capability without requiring a proportionally thick dielectric layer, thereby avoiding the manufacturing difficulties associated with handling excessively thick dielectric layers.
3Stability of the object's composition
If the dielectric layer thickness is reduced to minimize stress, then wafer warping is reduced, but the metal layer thickness must also be reduced which limits power supply capability
Solution Approach 1:
The dielectric layer is segmented with recesses (trenches) that are strategically positioned and filled with metal material. This segmentation allows the overall dielectric layer thickness to be reduced, minimizing thin film stress and preventing wafer warping, while the metal layer thickness in the recess regions can be increased to maintain or improve power supply capability. The metal is concentrated where it is most needed rather than being distributed throughout a thick dielectric layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the metal layer thickness, reduces the dielectric layer impact, improves power supply performance, and facilitates subsequent packaging by minimizing stress and warping, while maintaining overall chip performance.
Implementation Method 1
a back surface of the chip substrate is etched
Implementation Method 2
the first thin film is deposited on the back surface of the etched chip substrate
Implementation Method 3
the first thin film is deposited on the back surface of the etched chip substrate
Data Source
AI summary
A chip includes a chip substrate having a first thickness and including a back surface. The back surface includes an etched portion with an etching depth that is less than the first thickness. The chip further includes a first thin film including a dielectric material and located on the back surface. The chip further includes a second thin film including a barrier layer material and located on the first thin film. The chip further includes a third thin film including a metal material, embedded in the chip substrate, and located on the second thin film. The chip further includes a coverage layer including nitride or carbon nitride and located on the first thin film, the second thin film, and the third thin film.


