Stacked Semiconductor Chip Bonding With Roughness-Controlled Wetting
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Solution Overview
Problem
In semiconductor arrangements with stacked chips, the upper chip may 'float' due to bonding material viscosity issues, leading to short circuits or incorrect electrical contact, as the wire bonding machine cannot reach the upper chip if it is not positioned correctly.
Innovation Solution
A metallization layer with increased roughness along the contour of the upper semiconductor chip is applied, limiting the wetting of the bonding material to a region below the upper chip, preventing it from floating and ensuring correct positioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding material is applied to fasten the upper semiconductor chip, then the upper chip is secured to the lower chip, but the bonding material may cause the upper chip to float and leave its intended position
Solution Approach 1:
The metallization layer is given different surface properties in different regions: a first region with lower roughness where bonding material should spread, and a second region with higher roughness where bonding material should be restricted. This local differentiation of surface quality controls the bonding material's wetting behavior to prevent chip floating while ensuring proper positioning.
2Ease of manufacture
If the bonding material has low viscosity for easy application, then the bonding material spreads easily, but it may spread beyond the intended region and cause positioning errors
Solution Approach 1:
The metallization layer presents different surface roughness characteristics in different regions, creating localized wetting preferences that guide the bonding material's spread pattern. This allows easy application with low-viscosity materials while maintaining precise spread control through the surface structure gradient.
Solution Approach 2:
The surface roughness parameter of the metallization layer is varied spatially to control bonding material behavior. By changing the roughness parameter from low in the first region to high in the second region, the patent controls the wetting and spreading characteristics of the bonding material without requiring changes to the material's viscosity or application process.
3Manufacturing precision
If the metallization layer has high roughness to restrict bonding material spread, then positioning accuracy is improved, but the overall bonding area is reduced
Solution Approach 1:
Rather than making the entire metallization layer rough, only a specific second region adjacent to the semiconductor chip structure is given high roughness. The first region maintains lower roughness to provide adequate bonding area, while the localized high-roughness second region provides the positioning control function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents the upper semiconductor chip from floating, ensuring proper electrical contact and avoiding short circuits by restricting the bonding material's spread with a structured metallization layer, thus enhancing the reliability of semiconductor arrangements.
Implementation Method 1
wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by the structure to a region below the upper semiconductor chip
Data Source
AI summary
A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.