Chip Carrier Pad Offset Layout for High-Voltage Die Isolation
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Solution Overview
Problem
Cooling of semiconductor packages, particularly for high temperature compound semiconductors like GaN and SiC, is inadequate due to limited metal content and suboptimal chip-to-package ratios, which restricts performance and efficiency.
Innovation Solution
A semiconductor package design featuring a carrier with contact structures, a semiconductor die attached to the carrier, and a metal plate of variable size based on thermal load, along with an encapsulant that surrounds the die, optimizing thermal performance and chip-to-package ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the amount of metal and interconnect area are increased to improve cooling performance, then thermal performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the cooling function by introducing separate cooling plates for different dies (e.g., high-power die and low-power die) rather than using a unified interconnect structure. This allows optimized thermal management for each die type without increasing overall device complexity, as each segment handles its own thermal load independently.
Solution Approach 2:
The patent introduces cooling plates as intermediary thermal management components between the dies and the heat sink. These cooling plates serve as dedicated thermal pathways that improve cooling performance without requiring increased metal content in the interconnect structures, thus resolving the contradiction between thermal performance and device complexity.
2Use of energy by moving object
If chip size is reduced to improve efficiency for compound semiconductors, then power efficiency improves, but chip-to-package ratio deteriorates due to creepage distance requirements
Solution Approach 1:
The patent applies local quality by providing enhanced creepage protection specifically at high-voltage interfaces where needed, rather than uniformly increasing package size. The cooling plates and encapsulant structure provide localized electrical isolation that maintains adequate chip-to-package ratios while preserving power efficiency.
Solution Approach 2:
The patent addresses creepage distance requirements by transitioning to a three-dimensional packaging structure with encapsulant and stacked cooling plates, rather than relying solely on two-dimensional package area expansion. This vertical dimensionality allows maintained chip-to-package ratios while satisfying electrical clearance requirements.
3Ease of manufacture
If uniform cooling structure is used for all dies, then manufacturing simplicity is maintained, but thermal performance deteriorates for high-power applications
Solution Approach 1:
The patent implements local quality by providing different cooling plate configurations for different die types within the same package. High-power dies receive dedicated cooling plates with appropriate thermal conductivity and surface area, while low-power dies use different cooling structures. This differentiated approach optimizes thermal performance for each die type without significantly complicating manufacturing.
Solution Approach 2:
The cooling plate structure serves multiple functions: it provides thermal management for different die types, acts as an electrical isolation layer, and serves as a mechanical support structure. This multi-functionality allows differentiated cooling without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances thermal performance and chip-to-package ratios, enabling better heat dissipation and improved efficiency for high-power semiconductor applications.
Implementation Method 1
a metal plate attached to a second side of the semiconductor die, the metal plate having a size that is independent of a size of the carrier and based on an expected thermal load to be presented by the semiconductor die
Data Source
AI summary
A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.