Chip Carrier Substrate Capacitor Aperture Microloading Etch
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Solution Overview
Problem
Current chip carrier substrates face limitations in performance enhancements, particularly in achieving narrower linewidth and shallower depth for capacitor apertures during plasma etching, which affects connectivity and signal processing in microelectronic circuits.
Innovation Solution
The method involves using a plasma etch process that exploits the microloading effect to simultaneously form a capacitor aperture with a narrower linewidth and shallower depth compared to a via aperture, allowing for the precise placement and formation of capacitors and vias within the chip carrier substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plasma etching is used to form capacitor apertures and via apertures, then connectivity and signal processing are improved, but the linewidth and depth control for capacitor apertures deteriorates
Solution Approach 1:
The patent applies local quality by providing different aperture characteristics for different locations in the substrate. Capacitor apertures are formed with narrower linewidth and shallower depth, while via apertures have wider linewidth and greater depth. This is achieved through the microloading effect in plasma etching, where etch rate varies based on local aperture dimensions and spacing, allowing precise control of each aperture type's geometry to meet specific electrical and structural requirements.
2Adaptability or versatility
If additional conductor layers and dielectric layers are added to chip carrier substrates, then connectivity and power distribution are enhanced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a chip carrier substrate that integrates multiple functions within a unified structure. The substrate incorporates capacitor apertures, via apertures, conductor layers, and dielectric layers in a single multi-layer configuration that simultaneously provides connectivity, power distribution, and signal processing capabilities. This multi-functional integration enhances adaptability while managing complexity through a systematic layering approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of chip carrier substrates by improving connectivity and signal processing capabilities through precise aperture formation, enabling better integration with semiconductor chips and higher performance microelectronic circuits.
Implementation Method 1
The methods for fabricating the chip carrier substrate take advantage of a microloading effect when plasma etching within the chip carrier substrate: (1) a first aperture into which is located a capacitor; and (2) a second aperture into which is located a via. The microloading effect within the plasma etch method provides the first aperture with both a narrower linewidth and a more limited depth than the second aperture.
Implementation Method 2
The methods for fabricating the chip carrier substrate take advantage of a microloading effect when plasma etching within the chip carrier substrate
Data Source
AI summary
A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.