Chip Carrier With Via-Based 3D Integration
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Solution Overview
Problem
The integration of active and passive components in radio frequency semiconductors is hindered by electromagnetic interference, leading to increased device size and performance issues, as passive components must be spaced significantly away from active components and their interconnects to minimize electrical influence, while conventional methods fail to compactly integrate these components effectively.
Innovation Solution
A substrate with a ground plane and vias that electrically connect two sides, where passive components are formed on one side free of the ground plane and active components are attached, with printed wires and solder bumps used to connect them, allowing for reduced spacing and enhanced thermal conduction through coaxial via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If passive components are positioned close to active components to reduce device size, then device size is reduced, but electromagnetic interference and parasitic capacitance increase, degrading performance
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking, placing passive components on the bottom surface of the substrate while active components are mounted on the top surface. This dimensional separation allows components to be in close physical proximity (reducing device footprint) while maintaining electrical isolation through the substrate thickness, thereby resolving the contradiction between compact size and electromagnetic interference reduction.
Solution Approach 2:
The substrate acts as an intermediary element between passive and active components. It provides both mechanical support and electrical isolation, allowing the passive components to be positioned close to active components without direct electromagnetic coupling. The substrate's ground plane and via structures serve as intermediate pathways that manage signal routing while maintaining isolation.
2Object-affected harmful factors
If bonding wires are increased in number to reduce electrical influence, then electrical influence is reduced, but device size increases due to space requirements between wires
Solution Approach 1:
The patent replaces the mechanical bonding wire system with printed circuit board traces and via structures integrated into the substrate. This substitution eliminates the need for numerous discrete bonding wires while providing equivalent or superior electrical connection capabilities. The printed traces can be routed optimally without the spatial constraints of wire bonding, reducing both wire count and device area.
Solution Approach 2:
The patent merges multiple functions into the substrate structure: electrical connection, signal routing, and mechanical support. By integrating these functions into the substrate rather than using separate bonding wires and mounting structures, the design reduces the number of interconnect elements needed while maintaining electrical performance.
3Adaptability or versatility
If interconnects and contact pads are increased to connect more components, then component integration is improved, but interconnect crowding increases causing detrimental effects
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) to separate interconnect layers. By routing signals through vias that penetrate the substrate and using multi-layer PCB techniques, the design provides additional interconnection pathways without increasing planar crowding. This allows more components to be integrated while maintaining manageable interconnect complexity through vertical routing options.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces electromagnetic interference, allows for more compact integration of passive and active components, and maintains device performance by minimizing the effects of parasitic capacitance and electromagnetic coupling, while enabling increased connectivity without enlarging the device.
Implementation Method 1
A via that electrically connects the first side to the second side is formed
Implementation Method 2
enhanced thermal conduction through coaxial via structures
Implementation Method 3
reduces electromagnetic interference, allows for more compact integration of passive and active components, and maintains device performance by minimizing the effects of parasitic capacitance and electromagnetic coupling
Data Source
AI summary
A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of the ground plane. An active component is attached to the first side.