Chip-to-Chip Clocking Architecture for Mixed Sync-Async Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip-to-chip (C2C) interfaces are constrained by the limited area available for signal transmission, leading to bandwidth limitations and the need for high-speed data transmission. Additionally, these interfaces are typically specific to a particular implementation and do not support multiple C2C modes.
Innovation Solution
The implementation of a chip-to-chip interface that communicates both an interface clock signal and a logic clock signal between IC chips. The interface clock signal is synchronous with a data signal, while the logic clock signal is asynchronous and independent from the data signal, allowing for flexible communication modes and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single synchronous clock signal is used for data transmission, then data synchronization is achieved, but the interface cannot support multiple C2C modes and lacks flexibility
Solution Approach 1:
The clocking architecture is segmented into two independent clock signals: a first clock signal for data transmission and a second clock signal for logic operations. This segmentation allows each clock signal to be optimized for its specific function, enabling support for multiple C2C modes without requiring a complete redesign of the clocking system for each mode.
Solution Approach 2:
The interface is designed with universal clocking capability by incorporating both a first clock signal input and a second clock signal input, along with multiplexers that can selectively route either clock signal to the logic elements. This multi-functionality allows the same interface hardware to support multiple C2C communication modes (synchronous, asynchronous, burst modes) without requiring mode-specific hardware changes.
2Reliability
If the clock signal is derived from the data signal, then synchronization is maintained, but reliability decreases when data errors occur
Solution Approach 1:
The second clock signal is extracted as an independent input from the data signal path. By taking the clock signal out of the data-dependent generation process and providing it as a separate synchronized clock input, the system ensures that logic operations can continue reliably even when data errors occur, as the clock signal is not corrupted by data transmission issues.
3Productivity
If high data rate is used to achieve required bandwidth, then bandwidth requirements are met, but the interface area constraint becomes more challenging
Solution Approach 1:
The system changes the timing parameters of data transmission by supporting multiple clock rates through the two clock signal architecture. By being able to operate at different clock frequencies and modes (synchronous/asynchronous), the interface can optimize data transmission efficiency without requiring additional physical interface resources, thereby maintaining high bandwidth within the constrained interface area.
Data Source
AI summary
An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.