Semiconductor Chip CMP Chemistry for Metal Impurity Yield Control
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Solution Overview
Problem
The existing manufacturing methods for semiconductor chips face challenges in achieving high manufacturing yield due to the presence of metal impurities in chemical liquids used in the process, leading to defects and decreased yield.
Innovation Solution
A manufacturing method for semiconductor chips that involves using a chemical liquid containing organic solvents and specific metal impurities like Fe, Cr, and Ni, within controlled concentration ranges, to optimize the chemical-mechanical polishing process and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chemical liquids are used in the manufacturing process, then the process can be performed with standard materials, but metal impurities in the chemical liquid cause defects and decrease manufacturing yield
Solution Approach 1:
The patent applies parameter changes by precisely controlling the concentration of metal impurities (Fe, Cr, Ni) in the chemical liquid within specific ranges (Fe: 0.01-100 ppb, Cr: 0.01-100 ppb, Ni: 0.01-100 ppb). This quantitative control transforms the chemical liquid from a source of defects into a controlled variable that improves manufacturing yield while maintaining process functionality.
Solution Approach 2:
The patent converts the previously harmful metal impurities into beneficial controlled additives. By introducing specific metal impurities (Fe, Cr, Ni) at controlled concentrations, the chemical liquid now provides both its original cleaning function and additional benefits such as improved adhesion, controlled etching rates, and enhanced polishing performance, thereby improving manufacturing yield.
2Length of moving object
If the metal interconnection is thinned to achieve local interconnection in multilayer structures, then the device performance is improved, but the manufacturing precision and yield decrease
Solution Approach 1:
The patent uses parameter changes by controlling metal impurity concentrations to achieve precise control over the chemical-mechanical polishing process. This enables better control of material removal rates and surface finish quality, which is critical when working with thinned metal interconnections in multilayer structures, thereby maintaining manufacturing precision despite reduced interconnection thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the manufacturing yield of semiconductor chips by controlling the concentration of metal impurities, reducing defects, and improving the precision of metal interconnections.
Implementation Method 1
a treatment in which the surface of the insulating layer filled with metal is flattened by performing chemical-mechanical polishing is performed
Data Source
AI summary
The present invention provides a manufacturing method of a semiconductor chip, in which the manufacturing yield is excellent, and a kit. According to the present invention, a manufacturing method of a semiconductor chip includes Process 1 of forming an insulating layer on a base material, Process 2 of forming a patterned resist film on the insulating layer, Process 3 of forming the insulating layer having an opening portion by etching the insulating layer with the patterned resist film as a mask, Process 4 of removing the patterned resist film, Process 5 of filling the opening portion of the insulating layer with metal, and Process 6 of performing chemical-mechanical polishing on the insulating layer filled with metal. In at least one process of Process 1 to Process 6, a chemical liquid which includes an organic solvent and metal impurities including at least one metal atom selected from the group consisting of a Fe atom, a Cr atom, a Ni atom, and a Pb atom, and in which the total content of the metal atom is 0.001 to 100 mass ppt is used.