Semiconductor Chip Edge Wiring for Crack Detection by Signal Delay
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Solution Overview
Problem
During the manufacturing process of semiconductor packages, semiconductor chips can develop cracks during dicing, which can lead to reduced quality and reliability over time, necessitating a method to detect defects such as cracks effectively.
Innovation Solution
A semiconductor chip and package that utilize a clock counter and oscillator to count clock signals and determine defects by analyzing the delay in signal transmission through a wiring structure, with a controller issuing test command signals and interpreting resultant signals to assess chip integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dicing is performed to separate semiconductor chips from wafers, then individual semiconductor chips can be obtained for packaging, but cracks may occur at the edges of the chips reducing quality and reliability
Solution Approach 1:
The patent applies preliminary action by performing defect detection before the chips are packaged and shipped. The detection circuit is built into the chip itself, allowing cracks and defects to be identified early in the manufacturing process, before the chips are installed in packages where they would be difficult to access and test.
Solution Approach 2:
The patent implements self-service by incorporating a self-diagnostic capability directly into each semiconductor chip. The detection circuit uses the chip's own internal resources (oscillator, clock counter, wiring structure) to automatically detect its own defects without requiring external testing equipment, enabling each chip to test itself during or after packaging.
2Reliability
If defect detection methods are added to semiconductor chips, then crack detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the detection circuit to perform multiple functions using the same components. The wiring structure serves both as a functional interconnect for normal chip operation and as a test path for defect detection. The clock counter and oscillator are used both for timing operations and for measuring signal propagation delays to detect cracks.
Solution Approach 2:
The patent implements self-service by using the chip's own internal resources for self-diagnosis. Rather than adding complex external testing equipment, the chip uses its existing wiring structure, oscillator, and counter capabilities to automatically detect its own defects, minimizing the addition of external complexity while maximizing detection capability.
3Measurement precision
If clock counter and oscillator are used to detect cracks by measuring signal delay, then detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by using the propagation time of electrical signals as a measurable parameter to detect physical defects. By measuring the time it takes for a clock signal to travel through the wiring structure (using the oscillator and clock counter), the system can detect changes in signal delay that indicate the presence of cracks or defects in the chip's internal structures.
Solution Approach 2:
The patent replaces mechanical inspection methods with electrical measurement techniques. Instead of using physical or mechanical means to detect cracks, the invention uses electrical signal propagation timing through the chip's wiring structure, substituting a mechanical inspection process with an electrical measurement system that is more precise and easier to automate.
Data Source
AI summary
A semiconductor chip includes a wiring structure arranged along an edge of the semiconductor chip; a clock counter configured to output a test signal to a first node of the wiring structure and receive the test signal from a second node of the wiring structure; and an oscillator configured to output a first clock signal to the clock counter, where the clock counter is configured to count a number of clocks of the first clock signal as a first count value from a first time in which the test signal is output to the first node of the wiring structure to a second time in which the test signal is received from the second node of the wiring structure, and output a first resultant signal to a controller based on the first count value.