Chip Embedded PCB Via Hole Precision and Thickness Reduction
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Solution Overview
Problem
Conventional chip embedded printed circuit boards face challenges in reducing substrate thickness and ensuring precise via hole formation, leading to connection failures and decreased yield and reliability due to position tolerances and the complexity of the laser drill method.
Innovation Solution
A chip embedded printed circuit board structure and manufacturing method that involves forming upper patterns connected to posts on an insulating layer and lower patterns by etching copper foil, with the insulating layer embedding a chip provided with posts, and using a polyimide insulating film and conductive posts like copper, aluminum, or solder, to simplify the process and eliminate the need for conventional via hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the laser drill method is used to form via holes, then via holes can be formed through the insulating layer, but position tolerance and connection failure occur due to chip position tolerance and laser drill tolerance
Solution Approach 1:
The via holes are formed at predetermined positions on the insulating layer before the chip is mounted. This preliminary action ensures that the via holes are positioned with high precision relative to the substrate geometry, eliminating the accumulation of tolerances that would occur if via holes were formed after chip mounting. The chip is then mounted in alignment with these pre-formed via holes, ensuring reliable electrical connections.
2Length of stationary object
If the conventional tape-based chip embedding method is used, then the chip can be positioned and embedded in the substrate, but the entire thickness of the substrate cannot be reduced
Solution Approach 1:
The conventional tape carrier package (TCP) structure is completely removed from the manufacturing process. Instead of embedding the chip in a perforated core substrate attached to a tape, the chip is directly mounted on the insulating layer of the substrate. This extraction of the tape-based embedding method eliminates the additional thickness contributed by the tape and associated structures, enabling significant substrate thinning while simplifying the manufacturing process.
3Area of stationary object
If multiple layers are used to increase surface area, then the printed circuit board can mount electronic parts at high density, but the substrate thickness increases
Solution Approach 1:
The via holes provide vertical interlayer connections that enable high-density mounting in the thickness dimension rather than requiring extensive lateral layering. By utilizing the Z-dimension for electrical connections through the substrate thickness, the design achieves high circuit density without proportionally increasing the lateral footprint or overall substrate thickness, effectively using the third dimension to solve the density problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the substrate thickness, enhances yield and reliability by direct electrical connections, and simplifies the manufacturing process, thereby achieving miniaturization and cost reduction.
Implementation Method 1
an insulating layer embedding a chip provided with posts at an upper part
Implementation Method 2
forming vias by filling the via hole with conductive material
Implementation Method 3
forming lower patterns by etching a copper foil after forming the insulating layer
Data Source
AI summary
The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.