Chip Embedded Substrate Internal Circuit Density
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Solution Overview
Problem
Existing chip embedded substrates face limitations in achieving high circuit density due to constraints in designing wiring layers, particularly in embedding chips within substrates, which hinders the miniaturization and lightness of electronic devices.
Innovation Solution
The solution involves designing internal circuit patterns within an insulating layer where the chip is embedded, with outer layer circuit patterns connected through vias, allowing for increased circuit density by forming internal and outer layer connections, and manufacturing this substrate by creating grooves in the insulating layers to accommodate the chip and stacking additional layers for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring layers are provided to upper and lower portions of a core layer with build-up process, then a multilayer substrate is completed, but high density of the wiring layer cannot be implemented
Solution Approach 1:
The patent applies dimensionality change by transitioning from traditional planar wiring layers to three-dimensional internal circuit patterns embedded within the insulating layer. The grooves are formed at different depths and orientations within the insulating material, allowing circuit traces to occupy vertical space rather than only horizontal plane, thereby achieving higher circuit density without increasing substrate footprint or complexity
2Area of moving object
If chips are embedded in cavities penetrating through the substrate, then size of electronic component is reduced, but the substrate thickness increases
Solution Approach 1:
The patent implements nesting by placing circuit patterns and chips within the volumetric space of the insulating layer rather than creating through-substrate cavities. The grooves are embedded within the insulating material matrix, with chip mounting surfaces and circuit traces nested at different depth levels, achieving compact integration without increasing overall substrate thickness
Data Source
AI summary
A chip embedded substrate includes: an insulating layer having outer layer circuit patterns provided on any one of an upper surface and a lower surface thereof; a chip embedded in the insulating layer; and internal circuit patterns included in the insulating layer and disposed between a height of a top surface of the chip and a height of a bottom surface thereof.