Chip-Embedded Substrate I/O Pin Fabrication via Solder Reflow
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Solution Overview
Problem
In surface-mount technology, the formation of solder voids under input/output (I/O) pins on chip-embedded substrates can lead to performance degradation in electronic devices, as these voids increase series resistance, compromising the rated device characteristics and threatening the manufacturer's reputation for producing high-performance devices.
Innovation Solution
The method involves applying a contact-distinct volume of solder to recessed contacts on the chip-embedded substrate, followed by temperature-cycling to induce solder reflow and machining the I/O pins to extend uniformly to a common height within specification tolerance, thereby minimizing unintended solder void trapping and assuming quality control by the manufacturer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional surface-mount assembly processes are used without pre-formed I/O pins, then the manufacturing process remains simple and cost-effective, but solder voids form under the I/O pins causing increased series resistance and performance degradation
Solution Approach 1:
The patent applies preliminary action by forming I/O pins on the chip-embedded substrate before the surface-mount assembly process. The method includes applying solder to contacts, temperature-cycling to induce reflow, and machining pins to extend exposed from the substrate. This pre-formation of I/O pins eliminates solder void trapping during subsequent assembly, resolving the contradiction by preparing the substrate in advance to prevent performance degradation while maintaining assembly simplicity.
2Reliability
If the manufacturer performs quality control for solder void prevention, then device performance and customer loyalty improve, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The manufacturer performs preliminary actions during substrate fabrication by applying solder to recessed contacts, temperature-cycling to induce reflow, and machining I/O pins to uniform height. This built-in quality control during manufacturing prevents solder void formation before the customer receives the substrate, improving reliability while actually simplifying the customer's manufacturing process by eliminating their need to perform additional quality control steps.
3Manufacturing precision
If I/O pins are machined to uniform height, then solder void trapping is minimized and device performance is ensured, but the manufacturing process requires additional machining steps
Solution Approach 1:
The patent performs preliminary machining of I/O pins to uniform height during substrate fabrication. The method includes machining each I/O pin to extend exposed from the substrate to a common height within specification tolerance. This preliminary precision machining ensures proper solder joint formation during subsequent assembly while the standardized process becomes part of the manufacturing routine, balancing precision requirements with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the surface-mount assembly process, reduces costs, and ensures consistent device performance by eliminating solder voids, thereby reinforcing customer loyalty and protecting the manufacturer's reputation for producing high-performance devices.
Implementation Method 1
temperature-cycling the CES to induce solder reflow and define an I/O pin for each one of the at least two contacts
Data Source
AI summary
Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.