Chip-Exposed Semiconductor Package with Exposed Backside
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor power devices face limitations in delivering high power while maintaining a small footprint and effective heat dissipation due to competing parameters, often sacrificing one for the others.
Innovation Solution
A chip-exposed semiconductor package is developed without external leads, where a metal backside layer and terminal structures are exposed through a molding compound, allowing for a larger chip size within the same footprint, enhancing power delivery and heat dissipation by reducing parasitic inductance and package resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a traditional semiconductor package with external leads is used, then the device can be mounted and connected, but the footprint is larger and power handling capability is limited
Solution Approach 1:
The patent transitions from a traditional lead-based package to a chip-exposed package where the chip backside is directly exposed through the molding compound. This dimensional change allows the chip to extend beyond the package body in the vertical dimension, eliminating the need for lateral lead extensions and reducing the footprint while maintaining power handling capability.
Solution Approach 2:
The patent extracts the leads from the package structure entirely, using the chip backside itself as the external connection interface. By removing the leads and exposing the chip backside through the molding compound, the design eliminates unnecessary components and reduces the overall footprint while improving power handling.
2Power
If the chip size is increased to improve power handling, then power delivery is enhanced, but the footprint and profile height increase
Solution Approach 1:
The patent allows the chip to extend vertically beyond the package body by exposing the chip backside through the molding compound. This enables larger chip sizes to be used for improved power delivery without increasing the lateral footprint, as the additional chip area is accommodated in the vertical dimension rather than expanding the package footprint.
3Reliability
If external leads are used for connection, then electrical connection is established, but parasitic inductance and resistance increase
Solution Approach 1:
The patent removes the leads entirely from the package structure and uses the chip backside metallization as the external connection interface. This extraction of leads eliminates the source of parasitic inductance and resistance associated with lead inductance, while maintaining reliable electrical connection through the chip's own metallization layers.
Solution Approach 2:
The molding compound acts as an intermediary that provides mechanical support and environmental protection while allowing the chip backside to be exposed. This enables direct connection to the chip metallization without leads, reducing parasitic effects while maintaining connection reliability through the molded structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased power handling capability with improved thermal dissipation and reduced parasitic inductance and resistance, maintaining a compact footprint by internalizing space typically used for external leads.
Implementation Method 1
plating a metal on a front side of a wafer comprising a plurality of chips thereon therefore forming a plurality of plating areas on a front face of each chip
Implementation Method 2
grinding a backside of the wafer to reduce a thickness of the wafer
Implementation Method 3
depositing a back metal layer on the backside of the wafer after grinding
Implementation Method 4
applying a layer of conductive adhesive material on said plurality of plating areas; mounting a chip with the front face of the chip adhering onto a front face of each of the plurality of paddle through the conductive adhesive material
Data Source
AI summary
A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.