Chip Fail Detection Circuit Using Common Error Bus
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Solution Overview
Problem
Debugging chip failures during the test stage is time-consuming and costly due to the lack of probe pads, necessitating an efficient method to detect and record chip failures.
Innovation Solution
A circuit design comprising a common error bus, fail detector modules, and a control center that receives data signals to determine chip failures, broadcasts fail codes on the common error bus when not busy, collects and stores these codes, and reports them upon request.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If debugging is performed without probe pads during chip test stage, then debugging can be conducted, but debugging time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by integrating fail detector modules and error bus infrastructure into the chip design before testing occurs. These components are pre-configured to automatically detect and record failures during normal operation, eliminating the need for time-consuming post-failure probe pad debugging. The fail detectors continuously monitor operational signals and capture failure information proactively, rather than waiting for external debugging equipment.
Solution Approach 2:
The error bus serves as an intermediary component that facilitates automatic failure information transmission from fail detector modules to external debugging equipment. This intermediary infrastructure enables failure data to be captured and transmitted without requiring direct physical access through probe pads, thus reducing debugging time while maintaining manufacturing simplicity.
2Productivity
If probe pads are added to enable debugging, then debugging efficiency improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The fail detector modules are designed with multi-functionality, serving both normal operational monitoring and failure detection functions. These modules utilize existing operational signals within the chip, eliminating the need for separate dedicated testing infrastructure or additional probe pads. The same hardware components support both regular chip operation and failure detection, reducing overall device complexity.
Solution Approach 2:
The chip performs self-diagnosis through integrated fail detector modules that automatically monitor operational signals and detect failures without requiring external debugging equipment or additional physical access points. The system serves itself by capturing and recording failure information internally, eliminating the need for complex external debugging infrastructure and reducing device complexity.
3Measurement precision
If comprehensive failure detection is implemented, then failure identification accuracy improves, but circuit complexity increases
Solution Approach 1:
The failure detection system is segmented into multiple independent fail detector modules, each responsible for monitoring specific operational signals or functional blocks. This segmentation allows comprehensive coverage of potential failure modes while keeping each individual detector module simple and manageable. Each module independently processes its designated signals and transmits failure information through the error bus, maintaining detection accuracy without requiring a monolithic complex circuit.
Data Source
AI summary
A circuit for detecting and recording chip fails according to one embodiment of the present invention comprises a common error bus, a plurality of fail detector modules and a control center. Each of the plurality of fail detector modules is configured to receive at least a data signal to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus when the common error bus is not busy. The control center is configured to record a fail code from the common error bus and to report the recorded fail code when required.