Error Detection/Correction TRIZ Cases

Periodic clock noise is detected per timeslot and corrected with controllable delay, reducing jitter and subharmonic noise in interleaved ADCs.

Read error counts trigger selective flash reference voltage updates, improving data accuracy while limiting latency and control overhead.

Multiple read voltages and ECC decoding help recover multi-bit flash data when narrow read margins cause frequent errors.

Toggle flip-flop logic replaces XOR trees for serial parity and checksum handling, cutting chip area and pin demand while preserving error detection.

Local synchronous divider circuits generate parallel clocks from shared serial clock and reset signals, fixing channel skew at 0.5 UI with less latency.

Each data word is XOR-linked to the previous word so a single parity bit can propagate discrepancies and expose tampering in microprocessor data streams.

ECC feedback shifts sense amplifier read windows to recover uncorrectable NVM bit errors and extend memory reliability over time.

A split-bank memory layout adds on-die ECC generation and checking to improve reliability without extra storage or separate ECC DRAM.

Adaptive ECC mode selection lets a memory controller support tagged and non-tagged memory, improving reliability without full tagged-memory cost.

Lee distance coding improves multi-level flash decoding by correcting more cell errors with fewer redundancy cells than binary BCH codes.

Shared SBD and LBD datapaths let one LDPC decoder handle low-rate error correction and high-rate convergence with less power and hardware.

Two read voltages track flash-cell threshold shifts through bit distribution analysis, improving read accuracy and reducing uncorrectable errors.

Rateless erasure coding spreads encoded blocks across storage entities to improve data availability without heavy replication overhead.

A two-step ECC scheme uses correction history to skip failed first-pass decoding, reducing read burden while protecting NAND flash data retention.

Refresh starts only when block error counts and processor resets exceed thresholds, reducing bad block risk and unnecessary NAND flash refreshes.

Generates ECC from dummy-padded partial sector data while storing only real data, improving flash storage efficiency without losing error correction.

By moving the time-domain interpolator ahead of the FDEQ, optical receivers correct ADC timing errors with lower hardware complexity.

A buffered on-chip ECC write path corrects and re-encodes codewords during writes to cut power overhead while preserving memory reliability.

Re-encoding decoded data and comparing parity bits catches undetected flash memory ECC errors without adding CRC overhead.

Parity comparison after ECC correction helps distinguish power-failure errors from cell defects in NAND flash reads, improving data accuracy.

When BCH correction is exceeded, parity-based recovery reconstructs failed data units to preserve flash memory data integrity.

When LDPC decoding stalls in trapping sets, post-processing flips selected inputs or messages to recover valid codewords and lower error floors.

Extra ECC stored in another block helps high-number NAND flash pages correct more bit errors and cut uncorrectable read failures.

Ambiguity detection targets symbols in unsatisfied LDPC checks to cut error floors while avoiding maximum-likelihood decoder complexity.

Soft-data reliability monitoring replaces stored test patterns to tune detector parameters faster while preserving usable storage area.

A tiered SEC-DED and DEC-TED scheme corrects common memory bit errors first, cutting read latency while preserving large-memory reliability.

A termination module stops non-binary LDPC decoding once a valid codeword is detected, cutting iterations, power use, and processing time.

Partial encoding of M bits within each P-bit symbol preserves flash memory capacity while correcting error-prone levels through error-pattern mapping.

Multiple algebraic parity phases and joint parity bits improve flash ECC capability while reducing decoding latency, complexity, and power.

By tolerating errors in less critical bits, the circuitry adapts voltage and clock settings to sustain performance without repair overhead.

Combining outer coding, parity generation, and inner ECC bits enables non-volatile memory to correct both one-directional and mixed errors.

By queuing only XORed parity bits and reusing encoder logic, memory controllers cut decoder area, power, and read latency.

Omitting variable-node updates cuts LDPC decoding complexity, storage, and latency while preserving bit-error performance at high speed.

BER-driven coding selection switches among error correction methods during transmission to maintain data integrity without unnecessary overhead.

Runtime-configurable ECC adjusts check-bit generation and error locating as memory reliability changes, balancing data protection and storage overhead.

Grouped flash pages use adjustable threshold voltages and ECC feedback to recover reads when error bits exceed correction limits.

When flash read errors exceed first ECC capacity, splitting write data into sub-data with added ECC layers improves read reliability.

Separating total parity bits from conventional check bits cuts ECC resource use while improving multiple, burst, and range error detection.

Out-of-order LDPC block processing cuts message memory use and raises throughput for irregular code decoding.

Multi-dimensional row and column coding improves non-volatile memory error recovery when rising error counts overwhelm conventional ECC.

Magic numbers and error codes are written by LBA to enable parallel setting checks and user data reads, cutting response delay and memory overhead.

ECC data is distributed across flash blocks so a failed page can be reconstructed without large buffers, preventing write error propagation.

Embedded repair data lets relay stations correct corrupted packet headers and forward real-time video without retransmission delays.

Orthogonal nibble encoding enables multiple writes between erase cycles while adding single-cell error detection and correction in non-volatile memory.

Dual ECC decoders switch by parity and decode outcome to improve BER while cutting decoding time and power in semiconductor data correction.

A zigzag layered LDPC schedule alternates forward and backward updates to cut decoding complexity, memory, and XOR overhead while preserving convergence.

A special autocratic node uses shared scrubbing slots to test local guardians in situ without interrupting time-triggered network operation.

Block coding, convolutional interleaving, and LDPC coding improve cable QAM throughput by spreading burst noise and correcting bit errors.

Dual redundant keeper cells use XOR error checking to detect corrupted sleep-state bits and force reliable wake-up from deep sleep.

Weighted variable and check node messages improve LDPC decoding while avoiding belief propagation complexity and node searches.