Flash Memory Error Correction Using Sub-Data ECC Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As flash memory devices increase in storage capacity, maintaining reliable performance becomes challenging due to the difficulty in effectively correcting errors, especially when the number of error bits exceeds the capacity of existing error correction codes.
Innovation Solution
A memory controller that analyzes read data and generates multiple units of sub-data, along with first and second error correction codes using the same algorithm, to correct errors in flash memory devices, particularly in cases where the number of error bits exceeds the initial error correction code's capacity, thereby improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage capacity of flash memory is increased, then storage capacity is improved, but error correction capability deteriorates
Solution Approach 1:
The patent divides data into multiple units and generates separate first and second ECC data for each unit. This segmentation allows the system to handle errors in larger storage capacities by treating them as manageable segments, resolving the contradiction between increased storage capacity and maintained error correction capability.
Solution Approach 2:
The patent introduces a new dimension to error correction by generating both first ECC data (for normal error correction) and second ECC data (for additional error correction capability). This multi-layered approach enables the system to maintain reliability in high-capacity storage by adding another dimension of error protection.
2Reliability
If number of error bits exceeds first ECC capacity, then error correction capability is improved by generating second ECC data, but device complexity increases
Solution Approach 1:
The patent implements a dynamic error correction approach where the system first attempts correction using first ECC data, and only generates second ECC data when the number of error bits exceeds the first ECC capacity. This dynamic adaptation avoids unnecessary complexity while maintaining enhanced error correction capability when needed.
Solution Approach 2:
The patent applies partial error correction using first ECC data for typical error cases, and only employs the additional second ECC data when necessary (excessive action) for cases where error bits exceed the first ECC capacity. This selective approach balances reliability improvement with complexity management.
Data Source
AI summary
A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.