Dual Keeper Cell XOR Checking for Deep Sleep Wake Recovery
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Solution Overview
Problem
Integrated circuit devices can become trapped in a non-recoverable deep sleep mode due to hardware faults, especially when keeper cells storing critical configuration and enable signals are corrupted by soft errors or transients, leading to an inability to wake up from the power-saving mode.
Innovation Solution
Implementing dual redundant keeper cells with error detection using XOR operations to store and verify logic levels, ensuring robust exit from deep sleep mode by detecting and correcting errors, and using a predefined wake-up configuration to force recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the integrated circuit device enters deep sleep mode to reduce power consumption, then power consumption is reduced, but the device may become trapped in a non-recoverable state due to hardware faults
Solution Approach 1:
The patent applies preliminary action by pre-establishing a forced wake-up configuration and pre-defining a fixed exit sequence before the device enters deep sleep mode. This ensures that if faults occur during sleep, the device can reliably exit without being trapped in a non-recoverable state, thus maintaining reliability while achieving power reduction.
Solution Approach 2:
The patent implements beforehand cushioning by implementing error detection mechanisms and forced wake-up configurations that prepare the system in advance to handle potential faults. This cushioning ensures that even if keeper cells are corrupted or faults occur during deep sleep, the device can recover, preventing total lock-up while maintaining low power operation.
2Reliability
If dual redundant keeper cells with error detection are implemented, then reliability of deep sleep exit is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the keeper cell functionality into pairs of redundant cells, where each pair handles specific configuration or enable signals. This segmentation allows independent error detection for each signal group, improving reliability while keeping the complexity modular and manageable through systematic organization.
Solution Approach 2:
The patent implements copying by creating redundant copies of keeper cells for critical signals. Each critical signal is stored in pairs of keeper cells, and XOR operations compare these copies to detect errors. This copying approach provides fault tolerance without requiring completely new architectural elements, thus improving reliability with controlled complexity increase.
3Measurement precision
If error detection is performed on keeper cells, then detection precision of faults is improved, but power consumption during sleep mode increases
Solution Approach 1:
The patent applies continuity of useful action by keeping the error detection logic in a low-power standby state rather than completely shutting it down. The XOR operations and error detection circuits remain powered but inactive during deep sleep, allowing immediate fault detection upon wake-up without requiring full re-initialization, thus maintaining detection precision with minimal power overhead.
Solution Approach 2:
The patent implements this principle by using simple XOR logic gates for error detection, which are computationally inexpensive and consume minimal power. The error detection mechanism uses basic logical operations rather than complex algorithms, providing adequate fault detection precision while keeping the power penalty during sleep mode minimal.
4Reliability
If a total reset is performed upon error detection, then reliability of error handling is improved, but loss of information in other keeper cells occurs
Solution Approach 1:
The patent applies taking out by extracting the error handling function from the global reset mechanism. Instead of performing a total system reset when errors are detected in keeper cells, the patent isolates the error handling to only the affected deep sleep exit function circuits. This allows reliable error handling for sleep mode while preserving external I/O logic levels and other data stored in unaffected keeper cells.
Solution Approach 2:
The patent implements local quality by applying error handling and forced wake-up configurations only to the specific circuits involved in deep sleep exit functionality. The error detection and correction mechanisms are localized to keeper cell pairs and their associated logic, rather than affecting the entire device. This ensures reliable error handling for sleep mode recovery while maintaining data integrity in other parts of the system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Guarantees a reliable exit from deep sleep mode and recovery from soft errors, preventing device lock-up by ensuring accurate configuration and enable signals, even in the presence of corruption, and allowing for correction of errors post-exit.
Implementation Method 1
An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error for that keeper cell pair.
Data Source
AI summary
A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.