NAND Flash ECC Parity Check for Power-Failure Error Detection
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Solution Overview
Problem
Semiconductor memory systems using NAND flash memories face accuracy issues due to threshold level variations caused by malfunctions or adjacent cell influences, leading to incorrect error correction by ECC circuits when errors exceed their correction range, particularly during power failures.
Innovation Solution
A semiconductor memory system with an ECC circuit that includes an ECC codec and an error location solving block, which compares parities generated in write and read modes to determine error correction possibilities and locate errors, allowing for accurate correction within or beyond the ECC's error correction range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC circuit corrects errors using parity bits, then data accuracy is improved, but when errors exceed correction range the ECC circuit incorrectly identifies them as memory cell defects rather than power failure events
Solution Approach 1:
The patent performs a preliminary check by comparing the parity of corrected data with the original parity before finalizing correction. This preliminary action detects whether the correction was successful or if the error exceeded the correction range, preventing misidentification of power failure events as memory cell defects.
Solution Approach 2:
The patent implements a feedback mechanism where the corrected data is re-encoded and its parity is compared with the stored parity. This feedback loop verifies whether the correction was appropriate, allowing the system to distinguish between correctable errors and uncorrectable errors caused by power failures.
2Reliability
If ECC circuit performs error correction on all read data, then data accuracy is improved, but system complexity and processing time increase
Solution Approach 1:
The patent applies partial action by performing full error correction only when needed, using a quick parity comparison to determine whether correction is necessary. This avoids unnecessary correction operations and reduces system complexity while maintaining data accuracy when errors are present.
3Reliability
If ECC circuit corrects multiple bit errors, then data recovery is improved, but the circuit may incorrectly correct errors caused by power failure leading to data loss
Solution Approach 1:
The patent performs a preliminary verification step by re-encoding corrected data and comparing its parity with the original parity. This preliminary action ensures that corrections are only accepted when they are valid, preventing incorrect corrections of power failure errors and maintaining correction precision.
Data Source
AI summary
A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.